Simulation Results: aes/gcm_masked

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.33 %
  • code
  • 95.27 %
  • assert
  • 98.29 %
  • func
  • 65.44 %
  • block
  • 95.73 %
  • line
  • 97.47 %
  • branch
  • 89.44 %
  • toggle
  • 98.05 %
  • FSM
  • 96.13 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 80.766us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 149.847us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 63.213us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 81.849us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 159.299us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 203.866us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 85.390us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 81.849us 1 1 100.00
aes_csr_aliasing 2.000s 203.866us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 149.847us 1 1 100.00
aes_config_error 3.000s 84.604us 1 1 100.00
aes_stress 5.000s 317.572us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 149.847us 1 1 100.00
aes_config_error 3.000s 84.604us 1 1 100.00
aes_stress 5.000s 317.572us 1 1 100.00
back2back 2 2 100.00
aes_stress 5.000s 317.572us 1 1 100.00
aes_b2b 4.000s 106.107us 1 1 100.00
backpressure 1 1 100.00
aes_stress 5.000s 317.572us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 149.847us 1 1 100.00
aes_config_error 3.000s 84.604us 1 1 100.00
aes_stress 5.000s 317.572us 1 1 100.00
aes_alert_reset 8.000s 994.153us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 65.770us 1 1 100.00
aes_config_error 3.000s 84.604us 1 1 100.00
aes_alert_reset 8.000s 994.153us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 130.069us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 714.965us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 1563.382us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 8.000s 994.153us 1 1 100.00
stress 1 1 100.00
aes_stress 5.000s 317.572us 1 1 100.00
sideload 2 2 100.00
aes_stress 5.000s 317.572us 1 1 100.00
aes_sideload 2.000s 121.785us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 75.776us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 3.000s 112.505us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 7.000s 76.897us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 56.539us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 234.412us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 234.412us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 63.213us 1 1 100.00
aes_csr_rw 2.000s 81.849us 1 1 100.00
aes_csr_aliasing 2.000s 203.866us 1 1 100.00
aes_same_csr_outstanding 3.000s 135.039us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 63.213us 1 1 100.00
aes_csr_rw 2.000s 81.849us 1 1 100.00
aes_csr_aliasing 2.000s 203.866us 1 1 100.00
aes_same_csr_outstanding 3.000s 135.039us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 88.815us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 107.410us 1 1 100.00
aes_control_fi 1.000s 55.356us 1 1 100.00
aes_cipher_fi 6.000s 167.515us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 75.043us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 75.043us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 75.043us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 75.043us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 142.216us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1197.387us 1 1 100.00
aes_tl_intg_err 2.000s 710.059us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 710.059us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 8.000s 994.153us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 75.043us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 75.043us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 149.847us 1 1 100.00
aes_stress 5.000s 317.572us 1 1 100.00
aes_alert_reset 8.000s 994.153us 1 1 100.00
aes_core_fi 29.000s 10069.441us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 7.000s 76.897us 1 1 100.00
aes_config_error 3.000s 84.604us 1 1 100.00
aes_stress 5.000s 317.572us 1 1 100.00
aes_core_fi 29.000s 10069.441us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 75.043us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 59.127us 1 1 100.00
aes_stress 5.000s 317.572us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 5.000s 317.572us 1 1 100.00
aes_sideload 2.000s 121.785us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 59.127us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 59.127us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 59.127us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 59.127us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 59.127us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 5.000s 317.572us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 5.000s 317.572us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 107.410us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 107.410us 1 1 100.00
aes_control_fi 1.000s 55.356us 1 1 100.00
aes_cipher_fi 6.000s 167.515us 1 1 100.00
aes_ctr_fi 2.000s 75.757us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 107.410us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 107.410us 1 1 100.00
aes_control_fi 1.000s 55.356us 1 1 100.00
aes_cipher_fi 6.000s 167.515us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 6.000s 167.515us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 107.410us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 107.410us 1 1 100.00
aes_control_fi 1.000s 55.356us 1 1 100.00
aes_ctr_fi 2.000s 75.757us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 107.410us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 107.410us 1 1 100.00
aes_control_fi 1.000s 55.356us 1 1 100.00
aes_cipher_fi 6.000s 167.515us 1 1 100.00
aes_ctr_fi 2.000s 75.757us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 8.000s 994.153us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 107.410us 1 1 100.00
aes_control_fi 1.000s 55.356us 1 1 100.00
aes_cipher_fi 6.000s 167.515us 1 1 100.00
aes_ctr_fi 2.000s 75.757us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 107.410us 1 1 100.00
aes_control_fi 1.000s 55.356us 1 1 100.00
aes_cipher_fi 6.000s 167.515us 1 1 100.00
aes_ctr_fi 2.000s 75.757us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 107.410us 1 1 100.00
aes_control_fi 1.000s 55.356us 1 1 100.00
aes_ctr_fi 2.000s 75.757us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_ghash_fi 2.000s 56.482us 1 1 100.00
aes_fi 3.000s 107.410us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 107.410us 1 1 100.00
aes_control_fi 1.000s 55.356us 1 1 100.00
aes_cipher_fi 6.000s 167.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 4.000s 106.339us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 45966616668605989317307993724492268401556192385928147725863755984089052209885 162
UVM_INFO @ 10069441274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 115343518403165760641158278981159395821259172485030306709728472648204934985596 177
UVM_INFO @ 106339414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---