Simulation Results: aes/gcm_unmasked

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.89 %
  • code
  • 90.97 %
  • assert
  • 97.75 %
  • func
  • 62.96 %
  • block
  • 91.15 %
  • line
  • 93.14 %
  • branch
  • 84.12 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 119.429us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 120.066us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 83.789us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 80.772us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 151.522us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 86.725us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 118.989us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 80.772us 1 1 100.00
aes_csr_aliasing 2.000s 86.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 120.066us 1 1 100.00
aes_config_error 2.000s 91.071us 1 1 100.00
aes_stress 2.000s 240.301us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 120.066us 1 1 100.00
aes_config_error 2.000s 91.071us 1 1 100.00
aes_stress 2.000s 240.301us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 240.301us 1 1 100.00
aes_b2b 3.000s 150.368us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 240.301us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 120.066us 1 1 100.00
aes_config_error 2.000s 91.071us 1 1 100.00
aes_stress 2.000s 240.301us 1 1 100.00
aes_alert_reset 2.000s 145.311us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 80.144us 1 1 100.00
aes_config_error 2.000s 91.071us 1 1 100.00
aes_alert_reset 2.000s 145.311us 1 1 100.00
trigger_clear_test 0 1 0.00
aes_clear 1.000s 28.756us 0 1 0.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 507.990us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 145.311us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 240.301us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 240.301us 1 1 100.00
aes_sideload 2.000s 52.323us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 111.937us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 6.000s 911.442us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 80.043us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 348.278us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 348.278us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 83.789us 1 1 100.00
aes_csr_rw 1.000s 80.772us 1 1 100.00
aes_csr_aliasing 2.000s 86.725us 1 1 100.00
aes_same_csr_outstanding 2.000s 299.293us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 83.789us 1 1 100.00
aes_csr_rw 1.000s 80.772us 1 1 100.00
aes_csr_aliasing 2.000s 86.725us 1 1 100.00
aes_same_csr_outstanding 2.000s 299.293us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 6.000s 523.966us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 93.599us 0 1 0.00
aes_control_fi 2.000s 109.219us 1 1 100.00
aes_cipher_fi 2.000s 92.290us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 459.621us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 459.621us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 459.621us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 459.621us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 183.496us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 461.469us 1 1 100.00
aes_tl_intg_err 2.000s 167.729us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 167.729us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 145.311us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 459.621us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 459.621us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 120.066us 1 1 100.00
aes_stress 2.000s 240.301us 1 1 100.00
aes_alert_reset 2.000s 145.311us 1 1 100.00
aes_core_fi 2.000s 87.244us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 91.071us 1 1 100.00
aes_stress 2.000s 240.301us 1 1 100.00
aes_core_fi 2.000s 87.244us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 459.621us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 62.710us 1 1 100.00
aes_stress 2.000s 240.301us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 240.301us 1 1 100.00
aes_sideload 2.000s 52.323us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 62.710us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 62.710us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 62.710us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 62.710us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 62.710us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 240.301us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 240.301us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 93.599us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 93.599us 0 1 0.00
aes_control_fi 2.000s 109.219us 1 1 100.00
aes_cipher_fi 2.000s 92.290us 1 1 100.00
aes_ctr_fi 2.000s 103.973us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 93.599us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 93.599us 0 1 0.00
aes_control_fi 2.000s 109.219us 1 1 100.00
aes_cipher_fi 2.000s 92.290us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 92.290us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 93.599us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 93.599us 0 1 0.00
aes_control_fi 2.000s 109.219us 1 1 100.00
aes_ctr_fi 2.000s 103.973us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 93.599us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 93.599us 0 1 0.00
aes_control_fi 2.000s 109.219us 1 1 100.00
aes_cipher_fi 2.000s 92.290us 1 1 100.00
aes_ctr_fi 2.000s 103.973us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 145.311us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 93.599us 0 1 0.00
aes_control_fi 2.000s 109.219us 1 1 100.00
aes_cipher_fi 2.000s 92.290us 1 1 100.00
aes_ctr_fi 2.000s 103.973us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 93.599us 0 1 0.00
aes_control_fi 2.000s 109.219us 1 1 100.00
aes_cipher_fi 2.000s 92.290us 1 1 100.00
aes_ctr_fi 2.000s 103.973us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 93.599us 0 1 0.00
aes_control_fi 2.000s 109.219us 1 1 100.00
aes_ctr_fi 2.000s 103.973us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 93.599us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 93.599us 0 1 0.00
aes_control_fi 2.000s 109.219us 1 1 100.00
aes_cipher_fi 2.000s 92.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 7.000s 545.204us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_clear 26395702089541234021118992469539370389797492075950776932548007436679111831119 2080
TEST FAILED MESSAGES DID NOT MATCH
0 54 53 2c 0
1 7d 02 c2 0
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 9449609963642448333346439122237008259185834294682353402018062028968597182088 2994
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 1
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 37259725870159416652930677149380178255462566617161030115450390855973395671432 255
UVM_INFO @ 545204056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---