Simulation Results: clkmgr

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.95 %
  • code
  • 69.72 %
  • assert
  • 90.08 %
  • func
  • 65.04 %
  • line
  • 82.37 %
  • branch
  • 87.42 %
  • cond
  • 79.02 %
  • toggle
  • 99.81 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.240s 86.794us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.790s 24.591us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.580s 3.144us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.900s 283.887us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.540s 117.418us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.900s 9.992us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.580s 3.144us 0 1 0.00
clkmgr_csr_aliasing 1.540s 117.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.680s 15.897us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.170s 79.294us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.750s 26.971us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.240s 86.794us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.600s 4.856us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.610s 3.655us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.600s 4.856us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.760s 8.409us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.800s 28.003us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.090s 97.195us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.090s 97.195us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.790s 24.591us 1 1 100.00
clkmgr_csr_rw 0.580s 3.144us 0 1 0.00
clkmgr_csr_aliasing 1.540s 117.418us 1 1 100.00
clkmgr_same_csr_outstanding 0.750s 12.436us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.790s 24.591us 1 1 100.00
clkmgr_csr_rw 0.580s 3.144us 0 1 0.00
clkmgr_csr_aliasing 1.540s 117.418us 1 1 100.00
clkmgr_same_csr_outstanding 0.750s 12.436us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 13.760s 1846.408us 1 1 100.00
clkmgr_tl_intg_err 1.040s 39.759us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.570s 129.767us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.570s 129.767us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.570s 129.767us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.570s 129.767us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.270s 90.084us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.040s 39.759us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.600s 4.856us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.610s 3.655us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.570s 129.767us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.890s 154.686us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.580s 3.144us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 13.760s 1846.408us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.580s 3.144us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.580s 3.144us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 13.760s 1846.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.580s 4.627us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 3.040s 243.032us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 4 test runs
clkmgr_shadow_reg_errors_with_csr_rw 39747479652980867122119167514130345685651432717279460125646821874653647978511 80
UVM_INFO @ 90084112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 97320776353807269314664702909299176246681029883634607982323120597858452001238 136
UVM_INFO @ 39759233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 59854913653301146788308967789264954316776798879892481050918445880149799662838 80
UVM_INFO @ 3144286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 89783167090280849939518093726147119661017433983172298686546338151400368709591 81
UVM_INFO @ 9992169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency 34351008809839557493691717260120037268309602135886814672277941941912632546533 81
UVM_INFO @ 4855668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 96428055715433021005869475381160784355795905602873073664376660592485999924441 113
UVM_INFO @ 243032249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 38656612628763605114067027269688251544509150651508832383751583553056392741874 76
UVM_INFO @ 8409086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency_timeout 19851669915323531766375511795169127703984085302401934574714715842273057518184 82
UVM_INFO @ 3654874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 12860023713251320521563315505372077083354683465397696357813809541815724499189 79
UVM_INFO @ 4627383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 95532311916525266665597428767187121035845251233783928880152039448544743382663 80
UVM_INFO @ 283887195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 28398815806165946248236150184239665311304623731487003339627317360588558020023 80
UVM_INFO @ 12436405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---