Simulation Results: dma

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.30 %
  • code
  • 90.38 %
  • assert
  • 95.87 %
  • func
  • 63.64 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 1288.129us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 416.763us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 1405.956us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 79.514us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 21.053us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 5.000s 221.155us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 6.000s 2488.479us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 76.243us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 21.053us 1 1 100.00
dma_csr_aliasing 6.000s 2488.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 37.000s 80438.148us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 352.000s 86148.182us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 626.000s 133826.607us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 626.000s 133826.607us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 352.000s 86148.182us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 671.000s 73464.822us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 626.000s 133826.607us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 8.000s 886.223us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 118.000s 10119.152us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 15.992us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 11.800us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 541.986us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 541.986us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 79.514us 1 1 100.00
dma_csr_rw 1.000s 21.053us 1 1 100.00
dma_csr_aliasing 6.000s 2488.479us 1 1 100.00
dma_same_csr_outstanding 1.000s 101.108us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 79.514us 1 1 100.00
dma_csr_rw 1.000s 21.053us 1 1 100.00
dma_csr_aliasing 6.000s 2488.479us 1 1 100.00
dma_same_csr_outstanding 1.000s 101.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 20.000s 481.764us 1 1 100.00
dma_generic_stress 671.000s 73464.822us 1 1 100.00
dma_handshake_stress 626.000s 133826.607us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 1290.694us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 226.739us 1 1 100.00
dma_sec_cm 1.000s 13.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 74.000s 5516.655us 1 1 100.00
dma_longer_transfer 2.000s 125.450us 1 1 100.00
dma_stress_all_with_rand_reset 11.000s 873.272us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 18474679801739446566704777248209573717240916936609568437274492527064606711365 115
UVM_INFO @ 873271736ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---