Simulation Results: edn/edn0

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.94 %
  • code
  • 85.71 %
  • assert
  • 94.91 %
  • func
  • 50.21 %
  • block
  • 94.34 %
  • line
  • 97.12 %
  • branch
  • 87.81 %
  • toggle
  • 74.20 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 20.587us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 34.274us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 19.578us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 294.317us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 110.038us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 24.794us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 19.578us 1 1 100.00
edn_csr_aliasing 1.000s 110.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 179.588us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 179.588us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 179.588us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 20.877us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 318.325us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 180.174us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 12.771us 1 1 100.00
edn_disable_auto_req_mode 1.000s 36.300us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 5.000s 270.481us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 42.735us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 20.232us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 145.046us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 145.046us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 34.274us 1 1 100.00
edn_csr_rw 2.000s 19.578us 1 1 100.00
edn_csr_aliasing 1.000s 110.038us 1 1 100.00
edn_same_csr_outstanding 2.000s 26.631us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 34.274us 1 1 100.00
edn_csr_rw 2.000s 19.578us 1 1 100.00
edn_csr_aliasing 1.000s 110.038us 1 1 100.00
edn_same_csr_outstanding 2.000s 26.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.000s 1000.120us 1 1 100.00
edn_tl_intg_err 2.000s 141.330us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 64.095us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 318.325us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.000s 1000.120us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.000s 1000.120us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.000s 1000.120us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.000s 1000.120us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 318.325us 1 1 100.00
edn_sec_cm 6.000s 1000.120us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 318.325us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 141.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 16.000s 1681.848us 1 1 100.00