Simulation Results: edn/edn1

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.84 %
  • code
  • 83.55 %
  • assert
  • 97.14 %
  • func
  • 79.83 %
  • line
  • 98.25 %
  • branch
  • 93.72 %
  • cond
  • 90.31 %
  • toggle
  • 87.74 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.770s 28.652us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.740s 16.773us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.730s 47.660us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.550s 95.684us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 205.713us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.970s 56.975us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.730s 47.660us 1 1 100.00
edn_csr_aliasing 1.000s 205.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.540s 65.009us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.540s 65.009us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.540s 65.009us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.750s 22.673us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.960s 97.662us 1 1 100.00
errs 1 1 100.00
edn_err 0.810s 24.980us 1 1 100.00
disable 2 2 100.00
edn_disable 0.740s 12.986us 1 1 100.00
edn_disable_auto_req_mode 0.870s 36.056us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.670s 113.887us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 16.118us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.700s 23.662us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.770s 256.132us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.770s 256.132us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.740s 16.773us 1 1 100.00
edn_csr_rw 0.730s 47.660us 1 1 100.00
edn_csr_aliasing 1.000s 205.713us 1 1 100.00
edn_same_csr_outstanding 0.740s 25.369us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.740s 16.773us 1 1 100.00
edn_csr_rw 0.730s 47.660us 1 1 100.00
edn_csr_aliasing 1.000s 205.713us 1 1 100.00
edn_same_csr_outstanding 0.740s 25.369us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 1.990s 331.947us 1 1 100.00
edn_tl_intg_err 1.940s 129.030us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.760s 55.535us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.960s 97.662us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 1.990s 331.947us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 1.990s 331.947us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 1.990s 331.947us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 1.990s 331.947us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.960s 97.662us 1 1 100.00
edn_sec_cm 1.990s 331.947us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.960s 97.662us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.940s 129.030us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 22.720s 1433.016us 1 1 100.00