Simulation Results: entropy_src/rng_16bits

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 67.49 %
  • code
  • 82.21 %
  • assert
  • 74.06 %
  • func
  • 46.19 %
  • block
  • 94.08 %
  • line
  • 97.79 %
  • branch
  • 85.97 %
  • toggle
  • 52.36 %
  • FSM
  • 92.71 %
Validation stages
V1
83.33%
V2
93.75%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 44.265us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 74.574us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 55.149us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 4.000s 120.068us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 61.408us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 115.993us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 55.149us 1 1 100.00
entropy_src_csr_aliasing 3.000s 61.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 44.265us 1 1 100.00
entropy_src_rng 33.000s 13179.038us 1 1 100.00
entropy_src_fw_ov 132.000s 14206.637us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 132.000s 14206.637us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 33.000s 13179.038us 1 1 100.00
rng_max_rate 0 1 0.00
entropy_src_rng_max_rate 138.000s 4535.275us 0 1 0.00
health_checks 1 1 100.00
entropy_src_rng 33.000s 13179.038us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 33.000s 13179.038us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 33.000s 13179.038us 1 1 100.00
entropy_src_intr 11.000s 521.246us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 33.000s 13179.038us 1 1 100.00
entropy_src_functional_alerts 5.000s 691.317us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 137.000s 13277.822us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 283.496us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 63.666us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 16.816us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 239.744us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 89.634us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 89.634us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 74.574us 1 1 100.00
entropy_src_csr_rw 2.000s 55.149us 1 1 100.00
entropy_src_csr_aliasing 3.000s 61.408us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 23.470us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 74.574us 1 1 100.00
entropy_src_csr_rw 2.000s 55.149us 1 1 100.00
entropy_src_csr_aliasing 3.000s 61.408us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 23.470us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 99.441us 1 1 100.00
entropy_src_tl_intg_err 2.000s 190.791us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 33.000s 13179.038us 1 1 100.00
entropy_src_cfg_regwen 2.000s 16.876us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 33.000s 13179.038us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 33.000s 13179.038us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 33.000s 13179.038us 1 1 100.00
entropy_src_fw_ov 132.000s 14206.637us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 283.496us 1 1 100.00
entropy_src_sec_cm 2.000s 99.441us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 283.496us 1 1 100.00
entropy_src_sec_cm 2.000s 99.441us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 33.000s 13179.038us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 283.496us 1 1 100.00
entropy_src_sec_cm 2.000s 99.441us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 283.496us 1 1 100.00
entropy_src_sec_cm 2.000s 99.441us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 283.496us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 691.317us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 2.000s 190.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 121.000s 13094.463us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 13.000s 1435.332us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:2908) [scoreboard] Check failed match_found == * (* [*] vs * [*]) All candidate csrng seeds have been checked, with no match 1 test run
entropy_src_rng_max_rate 74761665853415483318008337496441821835346722682897962575751874080576529962766 1528
UVM_INFO @ 4535275141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 88810909722159424137530983378806438692162529589509630096400230034445331954184 122
UVM_INFO @ 1435331772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 21551575415685945871808465230598574460408161574806920777387046398311299242091 113
UVM_INFO @ 115993112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---