Simulation Results: hmac

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.05 %
  • code
  • 95.91 %
  • assert
  • 96.96 %
  • func
  • 29.28 %
  • block
  • 97.41 %
  • line
  • 98.35 %
  • branch
  • 93.52 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 11.000s 1158.234us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 27.839us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 85.505us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.000s 1365.198us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.000s 2176.341us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 56.817us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 85.505us 1 1 100.00
hmac_csr_aliasing 6.000s 2176.341us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 26.000s 4821.975us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 29.000s 1966.800us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.000s 228.544us 1 1 100.00
hmac_test_sha384_vectors 304.000s 14222.239us 1 1 100.00
hmac_test_sha512_vectors 21.000s 1281.698us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 354.201us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 2093.626us 1 1 100.00
hmac_test_hmac512_vectors 9.000s 318.113us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 18.000s 2000.333us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 233.000s 35982.359us 1 1 100.00
error 1 1 100.00
hmac_error 33.000s 4094.597us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 4.000s 3002.253us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 11.000s 1158.234us 1 1 100.00
hmac_long_msg 26.000s 4821.975us 1 1 100.00
hmac_back_pressure 29.000s 1966.800us 1 1 100.00
hmac_datapath_stress 233.000s 35982.359us 1 1 100.00
hmac_burst_wr 18.000s 2000.333us 1 1 100.00
hmac_stress_all 47.000s 18409.850us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 11.000s 1158.234us 1 1 100.00
hmac_long_msg 26.000s 4821.975us 1 1 100.00
hmac_back_pressure 29.000s 1966.800us 1 1 100.00
hmac_datapath_stress 233.000s 35982.359us 1 1 100.00
hmac_wipe_secret 4.000s 3002.253us 1 1 100.00
hmac_test_sha256_vectors 8.000s 228.544us 1 1 100.00
hmac_test_sha384_vectors 304.000s 14222.239us 1 1 100.00
hmac_test_sha512_vectors 21.000s 1281.698us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 354.201us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 2093.626us 1 1 100.00
hmac_test_hmac512_vectors 9.000s 318.113us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 11.000s 1158.234us 1 1 100.00
hmac_long_msg 26.000s 4821.975us 1 1 100.00
hmac_back_pressure 29.000s 1966.800us 1 1 100.00
hmac_datapath_stress 233.000s 35982.359us 1 1 100.00
hmac_burst_wr 18.000s 2000.333us 1 1 100.00
hmac_error 33.000s 4094.597us 1 1 100.00
hmac_wipe_secret 4.000s 3002.253us 1 1 100.00
hmac_test_sha256_vectors 8.000s 228.544us 1 1 100.00
hmac_test_sha384_vectors 304.000s 14222.239us 1 1 100.00
hmac_test_sha512_vectors 21.000s 1281.698us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 354.201us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 2093.626us 1 1 100.00
hmac_test_hmac512_vectors 9.000s 318.113us 1 1 100.00
hmac_stress_all 47.000s 18409.850us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 47.000s 18409.850us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 14.579us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 37.643us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 983.419us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 983.419us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 27.839us 1 1 100.00
hmac_csr_rw 1.000s 85.505us 1 1 100.00
hmac_csr_aliasing 6.000s 2176.341us 1 1 100.00
hmac_same_csr_outstanding 2.000s 39.475us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 27.839us 1 1 100.00
hmac_csr_rw 1.000s 85.505us 1 1 100.00
hmac_csr_aliasing 6.000s 2176.341us 1 1 100.00
hmac_same_csr_outstanding 2.000s 39.475us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 67.333us 1 1 100.00
hmac_tl_intg_err 2.000s 224.395us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 224.395us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 11.000s 1158.234us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 975.249us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 41.000s 18147.500us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 1427.565us 1 1 100.00