Simulation Results

Simulation Results: i2c

28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
89.05 %

code
90.57 %

assert
97.67 %

func
78.91 %

block
96.30 %

line
95.82 %

branch
93.39 %

toggle
86.73 %

FSM
86.33 %

Validation stages

V1		100.00%
V2		82.93%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	56.000s	3336.003us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	17.000s	978.316us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	125.576us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	43.416us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.000s	333.513us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	228.776us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	95.095us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	43.416us	1	1	100.00
	i2c_csr_aliasing	2.000s	228.776us	1	1	100.00

34/41 passed

82.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.000s	19.804us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	60.000s	5631.587us	0	1	0.00
host_maxperf				0	1	0.00
	i2c_host_perf	3600.000s	0.000us	0	1	0.00
host_override				1	1	100.00
	i2c_host_override	1.000s	57.028us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3600.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	514.000s	1608.304us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	244.739us	1	1	100.00
	i2c_host_fifo_fmt_empty	18.000s	1047.276us	1	1	100.00
	i2c_host_fifo_reset_rx	3.000s	759.710us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	279.000s	6330.403us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	8.000s	2240.783us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	3.000s	125.413us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.000s	467.619us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.000s	1450.665us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	21.000s	673.327us	1	1	100.00
	i2c_target_intr_smoke	6.000s	4604.468us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	265.497us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	316.591us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	1651.000s	35685.326us	1	1	100.00
	i2c_target_stress_rd	21.000s	673.327us	1	1	100.00
	i2c_target_intr_stress_wr	7.000s	14103.310us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	1298.423us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	2.000s	365.949us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	6.000s	1422.884us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	6.000s	10488.422us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.000s	876.059us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	142.759us	1	1	100.00
host_mode_config_perf				1	2	50.00
	i2c_host_perf	3600.000s	0.000us	0	1	0.00
	i2c_host_perf_precise	2.000s	492.307us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	8.000s	2240.783us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.000s	96.170us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	10411.001us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	1084.091us	1	1	100.00
	i2c_target_nack_txstretch	2.000s	185.481us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	2.000s	169.300us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	519.390us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	44.146us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	28.461us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	309.042us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	309.042us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	125.576us	1	1	100.00
	i2c_csr_rw	1.000s	43.416us	1	1	100.00
	i2c_csr_aliasing	2.000s	228.776us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	23.956us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	125.576us	1	1	100.00
	i2c_csr_rw	1.000s	43.416us	1	1	100.00
	i2c_csr_aliasing	2.000s	228.776us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	23.956us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	78.795us	1	1	100.00
	i2c_sec_cm	1.000s	50.474us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	78.795us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	46.000s	1745.340us	1
target_error_intr				1
	i2c_target_unexp_stop	1.000s	142.558us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	16.000s	844.609us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				3 test runs
	i2c_host_fifo_watermark	97498111573927775057016482898510059942605618079213642187602359057930654316656	None
	i2c_host_perf	30587739026788963176634813428691896193113104076988944220806469343001936065021	None
	i2c_target_stress_all	8212957465916271799290528974901873061812153197323187047396059980369535516394	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	114858615839462863566957958262135928615775992921494456895124421842421339545781	97	UVM_INFO @ 19804140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	93385214022900156749138305788944583868470853863185836000608611943379905552534	104	UVM_INFO @ 5631587379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	30937229311944449912060240059238514792798964294666688968826432728458045217923	101	UVM_INFO @ 1745339837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	59332885459931508334551246364217602862096101041436948993914854555557502379454	106	UVM_INFO @ 844609098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	76814162242511973020797063834912666973961100043864859180896503313471410895531	93	UVM_INFO @ 467618815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	73346336949314909052479985755609729431501243774998552909121909177820337930554	87	UVM_INFO @ 142557571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	110799902159173639456664880615678816797700308157219147351673834920631709218528	88	UVM_INFO @ 10488421740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---