| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| keymgr_dpe_smoke | 10.000s | 3809.956us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 2.000s | 64.642us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_rw | 2.000s | 46.966us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_bit_bash | 4.000s | 137.524us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_aliasing | 4.000s | 509.168us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_mem_rw_with_rand_reset | 2.000s | 130.831us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| keymgr_dpe_csr_rw | 2.000s | 46.966us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 4.000s | 509.168us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| intr_test | 1 | 1 | 100.00 | |||
| keymgr_dpe_intr_test | 1.000s | 18.820us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| keymgr_dpe_alert_test | 1.000s | 13.429us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| keymgr_dpe_tl_errors | 2.000s | 80.832us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| keymgr_dpe_tl_errors | 2.000s | 80.832us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 2.000s | 64.642us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_rw | 2.000s | 46.966us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 4.000s | 509.168us | 1 | 1 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 2.000s | 52.575us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 2.000s | 64.642us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_rw | 2.000s | 46.966us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 4.000s | 509.168us | 1 | 1 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 2.000s | 52.575us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| keymgr_dpe_sec_cm | 5.000s | 607.155us | 1 | 1 | 100.00 | |
| keymgr_dpe_tl_intg_err | 3.000s | 134.777us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 2.000s | 69.990us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 2.000s | 69.990us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 2.000s | 69.990us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 2.000s | 69.990us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors_with_csr_rw | 5.000s | 1546.119us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| keymgr_dpe_sec_cm | 5.000s | 607.155us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| keymgr_dpe_sec_cm | 5.000s | 607.155us | 1 | 1 | 100.00 | |