Simulation Results: lc_ctrl/volatile_unlock_disabled

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.70 %
  • code
  • 92.15 %
  • assert
  • 96.83 %
  • func
  • 86.13 %
  • block
  • 96.57 %
  • line
  • 97.29 %
  • branch
  • 91.26 %
  • toggle
  • 84.81 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.000s 61.363us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 25.640us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 48.845us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 67.507us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 22.777us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 21.295us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 48.845us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 22.777us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 73.232us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 319.592us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 22.985us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 47.775us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 1642.153us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 674.689us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 1642.153us 1 1 100.00
lc_ctrl_prog_failure 2.000s 47.775us 1 1 100.00
lc_ctrl_errors 4.000s 674.689us 1 1 100.00
lc_ctrl_security_escalation 3.000s 284.067us 1 1 100.00
lc_ctrl_jtag_state_failure 16.000s 10495.179us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 2631.968us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 2780.887us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 1419.556us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 421.058us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 2631.968us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 2780.887us 1 1 100.00
lc_ctrl_jtag_access 3.000s 2728.491us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 5.000s 722.340us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 92.020us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.000s 44.842us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 7563.781us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.000s 863.133us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 51.935us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 232.912us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 195.999us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 528.883us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 15.010us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 34.000s 23869.419us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 57.858us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 88.689us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 88.689us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 25.640us 1 1 100.00
lc_ctrl_csr_rw 1.000s 48.845us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 22.777us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 108.482us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 25.640us 1 1 100.00
lc_ctrl_csr_rw 1.000s 48.845us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 22.777us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 108.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 2.000s 425.191us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 113.105us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 113.105us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 319.592us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1642.153us 1 1 100.00
lc_ctrl_sec_cm 2.000s 425.191us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1642.153us 1 1 100.00
lc_ctrl_sec_cm 2.000s 425.191us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 1642.153us 1 1 100.00
lc_ctrl_sec_cm 2.000s 425.191us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 1642.153us 1 1 100.00
lc_ctrl_sec_cm 2.000s 425.191us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1642.153us 1 1 100.00
lc_ctrl_sec_cm 2.000s 425.191us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1642.153us 1 1 100.00
lc_ctrl_sec_cm 2.000s 425.191us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1642.153us 1 1 100.00
lc_ctrl_sec_cm 2.000s 425.191us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 1642.153us 1 1 100.00
lc_ctrl_sec_cm 2.000s 425.191us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.000s 284.067us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 73.232us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 421.058us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.000s 1626.454us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.000s 1626.454us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.000s 202.069us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 348.225us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 348.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.000s 1329.742us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 52337341922071757451912695510387583916595424169931118695862079481061084356203 211
UVM_INFO @ 1329741696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---