Simulation Results: mbx

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.66 %
  • code
  • 89.37 %
  • assert
  • 97.53 %
  • func
  • 76.07 %
  • block
  • 96.88 %
  • line
  • 96.71 %
  • branch
  • 91.89 %
  • toggle
  • 79.52 %
Validation stages
V1
83.33%
V2
90.91%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 70.000s 7892.154us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 29.027us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 15.705us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 174.559us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 77.572us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 4.161us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 15.705us 1 1 100.00
mbx_csr_aliasing 2.000s 77.572us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 129.000s 22168.624us 1 1 100.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 75.000s 10457.203us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 25.000s 3913.057us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 9.000s 3784.454us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 155.276us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 28.782us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 4.996us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 4.996us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 29.027us 1 1 100.00
mbx_csr_rw 1.000s 15.705us 1 1 100.00
mbx_csr_aliasing 2.000s 77.572us 1 1 100.00
mbx_same_csr_outstanding 1.000s 19.083us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 29.027us 1 1 100.00
mbx_csr_rw 1.000s 15.705us 1 1 100.00
mbx_csr_aliasing 2.000s 77.572us 1 1 100.00
mbx_same_csr_outstanding 1.000s 19.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 174.239us 1 1 100.00
mbx_sec_cm 2.000s 32.226us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 75131853381981516272771030869297550774040579841098818966402084869522696119435 85
TL item was: req: (cip_tl_seq_item@18852) { a_addr: 'h80f8b570 a_data: 'h271dd20c a_mask: 'h3 a_size: 'h1 a_param: 'h0 a_source: 'he3 a_opcode: 'h1 a_user: 'h25c95 d_param: 'h0 d_source: 'he3 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 4995919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 27159860236400396376569786410026978365626019234546678064237545416472063829130 86
TL item was: req: (cip_tl_seq_item@20890) { a_addr: 'hb27a95b4 a_data: 'hb7768ccb a_mask: 'h2 a_size: 'h2 a_param: 'h0 a_source: 'h64 a_opcode: 'h1 a_user: 'h269cd d_param: 'h0 d_source: 'h64 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 4160894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---