Simulation Results: otbn

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.21 %
  • code
  • 86.27 %
  • assert
  • 89.90 %
  • func
  • 97.46 %
  • block
  • 99.28 %
  • line
  • 99.47 %
  • branch
  • 94.74 %
  • toggle
  • 84.65 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 41.605us 1 1 100.00
single_binary 1 1 100.00
otbn_single 16.000s 41.691us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 18.654us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 26.278us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 55.328us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 56.571us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 72.688us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 26.278us 1 1 100.00
otbn_csr_aliasing 4.000s 56.571us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 58.000s 1488.965us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 19.000s 2307.769us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 23.000s 175.705us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 51.000s 247.714us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 85.000s 326.066us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 9.000s 154.336us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 7.000s 102.914us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 42.473us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 10.000s 186.403us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 73.743us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 19.566us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 63.103us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 63.103us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 18.654us 1 1 100.00
otbn_csr_rw 5.000s 26.278us 1 1 100.00
otbn_csr_aliasing 4.000s 56.571us 1 1 100.00
otbn_same_csr_outstanding 4.000s 19.967us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 18.654us 1 1 100.00
otbn_csr_rw 5.000s 26.278us 1 1 100.00
otbn_csr_aliasing 4.000s 56.571us 1 1 100.00
otbn_same_csr_outstanding 4.000s 19.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 11.000s 38.401us 1 1 100.00
otbn_dmem_err 6.000s 15.980us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 8.000s 21.471us 1 1 100.00
otbn_controller_ispr_rdata_err 7.000s 52.568us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 55.308us 1 1 100.00
otbn_urnd_err 5.000s 39.646us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 9.000s 42.666us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 53.880us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 22.016us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
otbn_tl_intg_err 23.000s 202.298us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 6.000s 74.280us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 41.605us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 6.000s 15.980us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 11.000s 38.401us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 23.000s 202.298us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 102.914us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 38.401us 1 1 100.00
otbn_dmem_err 6.000s 15.980us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 42.473us 1 1 100.00
otbn_illegal_mem_acc 9.000s 42.666us 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 16.000s 41.691us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 38.401us 1 1 100.00
otbn_dmem_err 6.000s 15.980us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 42.473us 1 1 100.00
otbn_illegal_mem_acc 9.000s 42.666us 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 102.914us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 38.401us 1 1 100.00
otbn_dmem_err 6.000s 15.980us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 42.473us 1 1 100.00
otbn_illegal_mem_acc 9.000s 42.666us 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 16.000s 41.691us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 19.374us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 41.992us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 35.000s 459.813us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 35.000s 459.813us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 50.687us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 104.741us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 79.402us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 79.402us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 51.611us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 16.000s 41.691us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 16.000s 41.691us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 16.000s 41.691us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 85.000s 326.066us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 16.000s 41.691us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 16.000s 41.691us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 30.813us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 16.000s 41.691us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 141.000s 1694.148us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 142.000s 4007.732us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 39.066us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 106424141028223566295974263236514797965855304357500032653587490791695310025721 91
UVM_INFO @ 74280222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---