Simulation Results: otp_ctrl

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.25 %
  • code
  • 72.83 %
  • assert
  • 94.09 %
  • func
  • 55.82 %
  • line
  • 87.46 %
  • branch
  • 84.04 %
  • cond
  • 85.81 %
  • toggle
  • 70.47 %
  • FSM
  • 36.37 %
Validation stages
V1
100.00%
V2
65.00%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.480s 86.594us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 9.860s 1078.533us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.390s 237.445us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.630s 104.617us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.040s 304.740us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.020s 401.849us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.310s 1314.218us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.630s 104.617us 1 1 100.00
otp_ctrl_csr_aliasing 5.020s 401.849us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.300s 70.576us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.260s 46.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 94.760s 7056.326us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.020s 310.738us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 2.200s 1180.298us 0 1 0.00
otp_ctrl_check_fail 8.310s 5783.637us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 1.590s 94.716us 0 1 0.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 6.050s 418.743us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 2.900s 1280.495us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 17.350s 11641.307us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 5.600s 348.535us 0 1 0.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 7.080s 918.099us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 20.440s 3298.377us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 14.660s 872.987us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.330s 47.999us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.640s 184.651us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.370s 288.644us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.370s 288.644us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.390s 237.445us 1 1 100.00
otp_ctrl_csr_rw 1.630s 104.617us 1 1 100.00
otp_ctrl_csr_aliasing 5.020s 401.849us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.860s 214.886us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.390s 237.445us 1 1 100.00
otp_ctrl_csr_rw 1.630s 104.617us 1 1 100.00
otp_ctrl_csr_aliasing 5.020s 401.849us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.860s 214.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
otp_ctrl_tl_intg_err 17.350s 1719.123us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 17.350s 1719.123us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 9.860s 1078.533us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 9.860s 1078.533us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
otp_ctrl_macro_errs 7.080s 918.099us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
otp_ctrl_macro_errs 7.080s 918.099us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.890s 259.028us 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.020s 310.738us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 8.310s 5783.637us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 6.050s 418.743us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 6.050s 418.743us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 6.050s 418.743us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 6.050s 418.743us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 6.050s 418.743us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 9.860s 1078.533us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 6.050s 418.743us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 9.860s 1078.533us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 237.710s 16567.690us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 1.590s 94.716us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 9.860s 1078.533us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 9.860s 1078.533us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 7.080s 918.099us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 60.590s 62929.289us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 17.100s 1090.463us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 3 test runs
otp_ctrl_dai_errs 40070001599586037920317126884444241254343905683765885180279652197044358745932 5275
UVM_INFO @ 348534721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 94995572804020089956146493249009384075904084161124677825642064811549303188485 2367
UVM_INFO @ 1280494907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 77137007036420638396726885912362812859237065775687183826685007091898410412545 16743
UVM_INFO @ 872986544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 38143923768878775112968111119926748555233406765340128273375428769052438369424 113122
UVM_INFO @ 7056325558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 12311119263786776551816827857152951386793642391907189631438139716286367153050 94
UVM_INFO @ 62929289460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:677) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_background_chks 115698176869165770480016145406376640374142716904336269838377489067628778054127 785
UVM_INFO @ 1180297691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 21587387988407322061243008599074087567500934824600808137388655885473096051270 7704
UVM_INFO @ 5783637220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_regwen 41644019870340379585462788854419750399008920969465954024507305078419289851144 297
UVM_INFO @ 94716394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 65753167981436705272034925235650364260199464047897746733300415113095107447864 5170
UVM_INFO @ 1090462888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---