Simulation Results: rom_ctrl/32kb

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.99 %
  • code
  • 83.01 %
  • assert
  • 96.80 %
  • func
  • 78.15 %
  • block
  • 86.67 %
  • line
  • 86.01 %
  • branch
  • 85.35 %
  • toggle
  • 84.48 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 1123.104us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 70.626us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 86.452us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 670.485us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 55.939us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 54.777us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 86.452us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 55.939us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 56.751us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.000s 64.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.000s 344.020us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 4.000s 114.250us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 2.000s 57.940us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 71.493us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 2.000s 61.079us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 2.000s 61.079us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 70.626us 1 1 100.00
rom_ctrl_csr_rw 2.000s 86.452us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 55.939us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 65.034us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 70.626us 1 1 100.00
rom_ctrl_csr_rw 2.000s 86.452us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 55.939us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 65.034us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 443.000s 1000000.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 3.000s 115.624us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 44.000s 452.860us 1 1 100.00
rom_ctrl_tl_intg_err 10.000s 111.507us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 44.000s 452.860us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 44.000s 452.860us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 443.000s 1000000.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 443.000s 1000000.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 443.000s 1000000.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 443.000s 1000000.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 443.000s 1000000.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 44.000s 452.860us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 44.000s 452.860us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 1123.104us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 1123.104us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 1123.104us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 10.000s 111.507us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 443.000s 1000000.000us 0 1 0.00
rom_ctrl_kmac_err_chk 2.000s 57.940us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 443.000s 1000000.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 443.000s 1000000.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 443.000s 1000000.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 3.000s 115.624us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 44.000s 452.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 2.000s 504.420us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 114488634448377007506033382035610524899700237732895719803095603085875706836666 88
UVM_INFO @ 344020202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rom_ctrl_corrupt_sig_fatal_chk 109612165571162700906730297992330734239710398526011645523885961706513091003148 88
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 1 test run
rom_ctrl_stress_all_with_rand_reset 29495240267762681074360818775366166099369540967751463871399297222470560546744 90
UVM_INFO @ 504419994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---