Simulation Results

Simulation Results: rv_dm/use_dmi_interface

28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.62 %

code
74.62 %

assert
96.59 %

func
94.64 %

block
90.19 %

line
89.88 %

branch
73.39 %

toggle
72.70 %

FSM
62.50 %

Validation stages

V1		96.30%
V2		73.91%
V2S		100.00%
V3		100.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	31.000s	1851.404us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	28.000s	161.307us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	28.000s	846.357us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	34.000s	12958.823us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	28.000s	198.538us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	29.000s	2792.184us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	29.000s	3054.582us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	30.000s	2600.318us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	91.000s	62637.944us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	29.000s	456.178us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	28.000s	392.556us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	29.000s	139.876us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	27.000s	91.236us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	29.000s	237.772us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	29.000s	916.934us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	29.000s	240.716us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	29.000s	618.788us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	29.000s	456.178us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	29.000s	163.940us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	28.000s	661.746us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	29.000s	139.876us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	28.000s	72.232us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	29.000s	78.792us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	30.000s	186.135us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	67.000s	37756.044us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	56.000s	4141.603us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	28.000s	61.889us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	56.000s	4141.603us	1	1	100.00
	rv_dm_csr_rw	30.000s	186.135us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	27.000s	70.536us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	27.000s	44.320us	1	1	100.00

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	31.000s	1851.404us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	30.000s	809.678us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	29.000s	330.256us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	28.000s	162.664us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	29.000s	438.976us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	38.000s	6337.025us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	28.000s	50.661us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	30.000s	6257.567us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	117.000s	65316.429us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	28.000s	271.243us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	31.000s	961.051us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	29.000s	910.900us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	28.000s	79.466us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	30.000s	12767.316us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	57.000s	12277.356us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	28.000s	346.725us	1	1	100.00
stress_all				1	1	100.00
	rv_dm_stress_all	34.000s	2713.287us	1	1	100.00
alert_test				1	1	100.00
	rv_dm_alert_test	28.000s	66.828us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	31.000s	1006.390us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	31.000s	1006.390us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	56.000s	4141.603us	1	1	100.00
	rv_dm_csr_hw_reset	29.000s	78.792us	1	1	100.00
	rv_dm_csr_rw	30.000s	186.135us	1	1	100.00
	rv_dm_same_csr_outstanding	31.000s	1196.899us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	56.000s	4141.603us	1	1	100.00
	rv_dm_csr_hw_reset	29.000s	78.792us	1	1	100.00
	rv_dm_csr_rw	30.000s	186.135us	1	1	100.00
	rv_dm_same_csr_outstanding	31.000s	1196.899us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	30.000s	877.912us	1	1	100.00
	rv_dm_tl_intg_err	32.000s	1076.137us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	32.000s	1076.137us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	31.000s	961.051us	1	1	100.00
	rv_dm_debug_disabled	28.000s	61.850us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	31.000s	961.051us	1	1	100.00
	rv_dm_debug_disabled	28.000s	61.850us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	31.000s	1851.404us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	29.000s	357.913us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	28.000s	68.523us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	28.000s	68.523us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	29.000s	357.913us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	rv_dm_stress_all_with_rand_reset	60.000s	4000.602us	1	1	100.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	494.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				3 test runs
	rv_dm_sba_tl_access	78855831825590776186982253029744456228165498729384336392629536720281555081008	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23804
	rv_dm_bad_sba_tl_access	72465684173409890237908954060575619400676943269337086022066835407041013251762	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23868
	rv_dm_autoincr_sba_tl_access	79574990160957120493274561259649087135224266328313082579472381393218146233502	141	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23732
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				1 test run
	rv_dm_delayed_resp_sba_tl_access	88932699166010542105751690969724453490829125207716699742619931099918178481205	107	UVM_INFO @ 50660598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	106879643694352245455274588919335165466623492705435133684241537702278222688801	87	UVM_INFO @ 91236207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	56111053858263918188995881320585990341993894740707362804617163383239547204989	87	UVM_INFO @ 79465958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	94736164608644953635020670329571963230695371082091453624022402360729945381574	87	UVM_INFO @ 271242951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	99094948418131707026875992607287774743553919691844597467594598068182451123475	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---