Simulation Results: rv_timer

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.29 %
  • code
  • 90.45 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 20.767us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 32.279us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 32.554us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 464.280us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 36.689us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 46.005us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 32.554us 1 1 100.00
rv_timer_csr_aliasing 1.000s 36.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 517.504us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 1297.792us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 65.000s 87798.649us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 65.000s 87798.649us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 5.000s 3730.680us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 41.938us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 42.010us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 99.021us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 99.021us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 32.279us 1 1 100.00
rv_timer_csr_rw 1.000s 32.554us 1 1 100.00
rv_timer_csr_aliasing 1.000s 36.689us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 66.415us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 32.279us 1 1 100.00
rv_timer_csr_rw 1.000s 32.554us 1 1 100.00
rv_timer_csr_aliasing 1.000s 36.689us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 66.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 607.699us 1 1 100.00
rv_timer_tl_intg_err 2.000s 150.490us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 150.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.000s 415.836us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 48.398us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 30.000s 6970.713us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 31744479056203930628551812669858321520797783845198099425536616028385320781816 85
UVM_INFO @ 415836291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 6225132592305774030790824314658656074267973890833168646918631480283171019496 84
UVM_INFO @ 517504276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 4552646918768812420259571134971208296692290042967847350714517910490603593597 84
UVM_INFO @ 48397772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---