Simulation Results: spi_device/1r1w

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.45 %
  • code
  • 89.47 %
  • assert
  • 95.40 %
  • func
  • 68.48 %
  • block
  • 98.38 %
  • line
  • 98.78 %
  • branch
  • 97.06 %
  • toggle
  • 72.46 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 15.000s 1816.541us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.000s 18.620us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 78.311us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 22.000s 18640.838us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 7.000s 210.901us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 1312.253us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 78.311us 1 1 100.00
spi_device_csr_aliasing 7.000s 210.901us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 14.161us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 150.553us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 72.396us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 1.780us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 7.086us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 7.000s 544.163us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 7.000s 544.163us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 9.000s 3408.615us 1 1 100.00
spi_device_tpm_sts_read 2.000s 45.671us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 15.000s 2327.676us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 6.000s 825.757us 1 1 100.00
spi_device_flash_all 137.000s 53956.015us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.000s 81.789us 1 1 100.00
spi_device_flash_all 137.000s 53956.015us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.000s 81.789us 1 1 100.00
spi_device_flash_all 137.000s 53956.015us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 137.000s 53956.015us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 10.000s 2013.424us 1 1 100.00
spi_device_flash_all 137.000s 53956.015us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 10.000s 2013.424us 1 1 100.00
spi_device_flash_all 137.000s 53956.015us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 10.000s 2013.424us 1 1 100.00
spi_device_flash_all 137.000s 53956.015us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 10.000s 2013.424us 1 1 100.00
spi_device_flash_all 137.000s 53956.015us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 10.000s 2013.424us 1 1 100.00
spi_device_flash_all 137.000s 53956.015us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.000s 48.798us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 56.000s 17323.299us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 56.000s 17323.299us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 56.000s 17323.299us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 4.000s 204.216us 1 1 100.00
spi_device_read_buffer_direct 3.000s 94.494us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 56.000s 17323.299us 1 1 100.00
spi_device_flash_all 137.000s 53956.015us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 137.000s 53956.015us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 137.000s 53956.015us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 104.243us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 104.243us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 86.000s 27437.317us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 15.000s 1816.541us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 75.000s 21100.934us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 14.000s 3322.191us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 15.844us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 48.825us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.000s 718.117us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.000s 718.117us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 18.620us 1 1 100.00
spi_device_csr_rw 3.000s 78.311us 1 1 100.00
spi_device_csr_aliasing 7.000s 210.901us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 181.715us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 18.620us 1 1 100.00
spi_device_csr_rw 3.000s 78.311us 1 1 100.00
spi_device_csr_aliasing 7.000s 210.901us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 181.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 398.031us 1 1 100.00
spi_device_tl_intg_err 17.000s 4362.435us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 17.000s 4362.435us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 13801602559759108212360176556106959197264475798758625990399967173908579792286 87
UVM_ERROR @ 1216685 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[914] not found within the scope .
UVM_ERROR @ 1216685 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[914] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 97092071119196975780693496527180110717733520849008615426208286936796087641389 85
UVM_ERROR @ 4703946 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1dd [111011101] vs 0x0 [0])
UVM_ERROR @ 4763946 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x188 [110001000] vs 0x0 [0])
UVM_ERROR @ 4807946 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1b6 [110110110] vs 0x0 [0])
UVM_ERROR @ 4834946 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x39b [1110011011] vs 0x0 [0])