Simulation Results: sram_ctrl/ret

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.55 %
  • code
  • 82.38 %
  • assert
  • 97.67 %
  • func
  • 94.60 %
  • block
  • 93.81 %
  • line
  • 94.91 %
  • branch
  • 89.64 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 233.498us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 16.029us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 83.266us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 57.359us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 176.098us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 33.483us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 83.266us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 176.098us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 3.000s 115.297us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 359.316us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 9.000s 420.389us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 119.000s 5983.458us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 4.000s 159.388us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 8.000s 1630.799us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.000s 464.529us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 6.000s 2654.609us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 38.183us 1 1 100.00
sram_ctrl_partial_access_b2b 122.000s 35686.675us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 112.135us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 28.400us 0 1 0.00
sram_ctrl_throughput_w_readback 1.000s 25.578us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 442.744us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 91.453us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 28.000s 4106.549us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 51.991us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 203.266us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 203.266us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.029us 1 1 100.00
sram_ctrl_csr_rw 1.000s 83.266us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 176.098us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 38.086us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.029us 1 1 100.00
sram_ctrl_csr_rw 1.000s 83.266us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 176.098us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 38.086us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 914.820us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 965.885us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 86.964us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 965.885us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 86.964us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 442.744us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 442.744us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 83.266us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 6.000s 2654.609us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 2654.609us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 2654.609us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.000s 464.529us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 42.606us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 914.820us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 34.917us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 233.498us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 233.498us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 6.000s 2654.609us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 965.885us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.000s 464.529us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 965.885us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 965.885us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 233.498us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 965.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 20.000s 7077.416us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 18380075805887645362273599782726720627890206325638856272954317649559719230375 86
UVM_INFO @ 112134609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 88359468064976126764529755805187809407092855134703002024849090941233808897914 86
UVM_INFO @ 28399765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 53884566678247571138478056804346191568534767212573878536519927759740435806848 86
UVM_INFO @ 25577721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---