Simulation Results: uart

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.83 %
  • code
  • 92.53 %
  • assert
  • 98.27 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.000s 551.707us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 21.592us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 60.158us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 142.834us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 34.989us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 105.903us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 60.158us 1 1 100.00
uart_csr_aliasing 2.000s 34.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 44.000s 83367.835us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.000s 551.707us 1 1 100.00
uart_tx_rx 44.000s 83367.835us 1 1 100.00
parity_error 2 2 100.00
uart_intr 43.000s 43546.069us 1 1 100.00
uart_rx_parity_err 31.000s 51764.648us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 44.000s 83367.835us 1 1 100.00
uart_intr 43.000s 43546.069us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 9.000s 27950.922us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 14.000s 44768.557us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 70.000s 147111.962us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 43.000s 43546.069us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 43.000s 43546.069us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 43.000s 43546.069us 1 1 100.00
perf 1 1 100.00
uart_perf 43.000s 9317.774us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.000s 9636.581us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.000s 9636.581us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 5.000s 7081.524us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 6.000s 45736.158us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.000s 1743.058us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 13.000s 5565.998us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 204.000s 87488.019us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 114.000s 243185.773us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 13.480us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 47.087us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 108.683us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 108.683us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 21.592us 1 1 100.00
uart_csr_rw 1.000s 60.158us 1 1 100.00
uart_csr_aliasing 2.000s 34.989us 1 1 100.00
uart_same_csr_outstanding 1.000s 20.195us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 21.592us 1 1 100.00
uart_csr_rw 1.000s 60.158us 1 1 100.00
uart_csr_aliasing 2.000s 34.989us 1 1 100.00
uart_same_csr_outstanding 1.000s 20.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 69.447us 1 1 100.00
uart_tl_intg_err 1.000s 315.003us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 315.003us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 29.000s 3473.838us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 28262545566347919963204076183776772672718810899729626621652308199456435975903 84
UVM_ERROR @ 6439244037 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 6439244037 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 6847224037 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 2 (+/-1), act: 29, clk_pulses: 0
UVM_ERROR @ 6847424037 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (52 [0x34] vs 255 [0xff]) reg name: uart_reg_block.rdata