Simulation Results: ac_range_check

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.76 %
  • code
  • 92.91 %
  • assert
  • 97.75 %
  • func
  • 57.61 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 19.000s 2926.015us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 34.000s 1562.914us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 36.836us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 1.000s 94.590us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 22.000s 728.590us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 20.000s 2798.497us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 20.932us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 1.000s 94.590us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 2798.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 25.430us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 18.000s 927.843us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 120.000s 25860.735us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 21.788us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 64.352us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 441.119us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 441.119us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 36.836us 1 1 100.00
ac_range_check_csr_rw 1.000s 94.590us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 2798.497us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 514.014us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 36.836us 1 1 100.00
ac_range_check_csr_rw 1.000s 94.590us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 2798.497us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 514.014us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 5940.606us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 5940.606us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 5940.606us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 5940.606us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 55.000s 1477.634us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 27.948us 1 1 100.00
ac_range_check_tl_intg_err 5.000s 204.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 216.000s 6922.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 26.000s 1423.777us 1 1 100.00