| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
94.44% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| aes_wake_up | 2.000s | 72.481us | 1 | 1 | 100.00 | |
| smoke | 1 | 1 | 100.00 | |||
| aes_smoke | 2.000s | 75.371us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aes_csr_hw_reset | 1.000s | 59.315us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aes_csr_rw | 2.000s | 83.949us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aes_csr_bit_bash | 5.000s | 855.262us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aes_csr_aliasing | 3.000s | 93.529us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aes_csr_mem_rw_with_rand_reset | 1.000s | 110.384us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aes_csr_rw | 2.000s | 83.949us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 3.000s | 93.529us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| algorithm | 3 | 3 | 100.00 | |||
| aes_smoke | 2.000s | 75.371us | 1 | 1 | 100.00 | |
| aes_config_error | 4.000s | 290.234us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| key_length | 3 | 3 | 100.00 | |||
| aes_smoke | 2.000s | 75.371us | 1 | 1 | 100.00 | |
| aes_config_error | 4.000s | 290.234us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| back2back | 2 | 2 | 100.00 | |||
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| aes_b2b | 13.000s | 978.157us | 1 | 1 | 100.00 | |
| backpressure | 1 | 1 | 100.00 | |||
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| multi_message | 4 | 4 | 100.00 | |||
| aes_smoke | 2.000s | 75.371us | 1 | 1 | 100.00 | |
| aes_config_error | 4.000s | 290.234us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| aes_alert_reset | 5.000s | 169.078us | 1 | 1 | 100.00 | |
| failure_test | 3 | 3 | 100.00 | |||
| aes_man_cfg_err | 2.000s | 76.469us | 1 | 1 | 100.00 | |
| aes_config_error | 4.000s | 290.234us | 1 | 1 | 100.00 | |
| aes_alert_reset | 5.000s | 169.078us | 1 | 1 | 100.00 | |
| trigger_clear_test | 1 | 1 | 100.00 | |||
| aes_clear | 3.000s | 103.339us | 1 | 1 | 100.00 | |
| nist_test_vectors | 1 | 1 | 100.00 | |||
| aes_nist_vectors | 9.000s | 493.638us | 1 | 1 | 100.00 | |
| nist_test_vectors_gcm | 1 | 1 | 100.00 | |||
| aes_nist_vectors_gcm | 8.000s | 753.023us | 1 | 1 | 100.00 | |
| reset_recovery | 1 | 1 | 100.00 | |||
| aes_alert_reset | 5.000s | 169.078us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| sideload | 2 | 2 | 100.00 | |||
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| aes_sideload | 2.000s | 63.900us | 1 | 1 | 100.00 | |
| deinitialization | 1 | 1 | 100.00 | |||
| aes_deinit | 2.000s | 101.145us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| aes_stress_all | 11.000s | 446.259us | 1 | 1 | 100.00 | |
| gcm_save_and_restore | 1 | 1 | 100.00 | |||
| aes_gcm_save_restore | 3.000s | 190.525us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aes_alert_test | 1.000s | 64.291us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 3.000s | 508.377us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 3.000s | 508.377us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 1.000s | 59.315us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 83.949us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 3.000s | 93.529us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 2.000s | 137.155us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 1.000s | 59.315us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 83.949us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 3.000s | 93.529us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 2.000s | 137.155us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reseeding | 1 | 1 | 100.00 | |||
| aes_reseed | 2.000s | 107.980us | 1 | 1 | 100.00 | |
| fault_inject | 2 | 3 | 66.67 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 240.112us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 87.973us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 103.191us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 103.191us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 103.191us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 103.191us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors_with_csr_rw | 6.000s | 2420.209us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| aes_sec_cm | 5.000s | 5685.554us | 1 | 1 | 100.00 | |
| aes_tl_intg_err | 2.000s | 452.208us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| aes_tl_intg_err | 2.000s | 452.208us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| aes_alert_reset | 5.000s | 169.078us | 1 | 1 | 100.00 | |
| sec_cm_main_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 103.191us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 103.191us | 1 | 1 | 100.00 | |
| sec_cm_main_config_sparse | 4 | 4 | 100.00 | |||
| aes_smoke | 2.000s | 75.371us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| aes_alert_reset | 5.000s | 169.078us | 1 | 1 | 100.00 | |
| aes_core_fi | 5.000s | 479.225us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_sparse | 4 | 4 | 100.00 | |||
| aes_gcm_save_restore | 3.000s | 190.525us | 1 | 1 | 100.00 | |
| aes_config_error | 4.000s | 290.234us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| aes_core_fi | 5.000s | 479.225us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 103.191us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_regwen | 2 | 2 | 100.00 | |||
| aes_readability | 2.000s | 68.072us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 2 | 2 | 100.00 | |||
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| aes_sideload | 2.000s | 63.900us | 1 | 1 | 100.00 | |
| sec_cm_key_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 68.072us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 68.072us | 1 | 1 | 100.00 | |
| sec_cm_key_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 68.072us | 1 | 1 | 100.00 | |
| sec_cm_iv_config_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 68.072us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 68.072us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_key_sca | 1 | 1 | 100.00 | |||
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| sec_cm_key_masking | 1 | 1 | 100.00 | |||
| aes_stress | 2.000s | 207.433us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_redun | 3 | 4 | 75.00 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 240.112us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 87.973us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 84.986us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| sec_cm_cipher_fsm_redun | 2 | 3 | 66.67 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 240.112us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 87.973us | 1 | 1 | 100.00 | |
| sec_cm_cipher_ctr_redun | 1 | 1 | 100.00 | |||
| aes_cipher_fi | 2.000s | 87.973us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| sec_cm_ctr_fsm_redun | 2 | 3 | 66.67 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 240.112us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 84.986us | 1 | 1 | 100.00 | |
| sec_cm_ghash_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_sparse | 3 | 4 | 75.00 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 240.112us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 87.973us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 84.986us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| aes_alert_reset | 5.000s | 169.078us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 3 | 4 | 75.00 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 240.112us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 87.973us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 84.986us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_local_esc | 3 | 4 | 75.00 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 240.112us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 87.973us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 84.986us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_local_esc | 2 | 3 | 66.67 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 240.112us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 84.986us | 1 | 1 | 100.00 | |
| sec_cm_ghash_fsm_local_esc | 1 | 2 | 50.00 | |||
| aes_ghash_fi | 2.000s | 49.445us | 1 | 1 | 100.00 | |
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| sec_cm_data_reg_local_esc | 2 | 3 | 66.67 | |||
| aes_fi | 4.000s | 247.671us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 240.112us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 87.973us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| aes_stress_all_with_rand_reset | 8.000s | 732.276us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] | 1 test run | |||
| aes_fi | 25194017563451264435941727848093229591415780015645220958849525980631992800741 | 16077 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) | 1 test run | |||
| aes_stress_all_with_rand_reset | 80242014764664929062309754021061895205786564980062158667962097006805299285039 | 250 |
UVM_INFO @ 732276438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|