Simulation Results: aes/gcm_unmasked

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.31 %
  • code
  • 90.65 %
  • assert
  • 97.94 %
  • func
  • 64.35 %
  • block
  • 89.97 %
  • line
  • 91.93 %
  • branch
  • 81.91 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.12%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 88.772us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 84.009us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 63.199us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 57.789us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 1264.840us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 549.571us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 90.935us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 57.789us 1 1 100.00
aes_csr_aliasing 3.000s 549.571us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 84.009us 1 1 100.00
aes_config_error 2.000s 90.569us 1 1 100.00
aes_stress 3.000s 69.528us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 84.009us 1 1 100.00
aes_config_error 2.000s 90.569us 1 1 100.00
aes_stress 3.000s 69.528us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 69.528us 1 1 100.00
aes_b2b 3.000s 135.001us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 69.528us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 84.009us 1 1 100.00
aes_config_error 2.000s 90.569us 1 1 100.00
aes_stress 3.000s 69.528us 1 1 100.00
aes_alert_reset 4.000s 552.422us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 109.709us 1 1 100.00
aes_config_error 2.000s 90.569us 1 1 100.00
aes_alert_reset 4.000s 552.422us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 111.675us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 1761.562us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 552.422us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 69.528us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 69.528us 1 1 100.00
aes_sideload 3.000s 95.544us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 639.568us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10802.112s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 162.371us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 91.063us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 91.063us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 63.199us 1 1 100.00
aes_csr_rw 1.000s 57.789us 1 1 100.00
aes_csr_aliasing 3.000s 549.571us 1 1 100.00
aes_same_csr_outstanding 2.000s 82.199us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 63.199us 1 1 100.00
aes_csr_rw 1.000s 57.789us 1 1 100.00
aes_csr_aliasing 3.000s 549.571us 1 1 100.00
aes_same_csr_outstanding 2.000s 82.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 6.000s 1807.101us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 3.000s 563.883us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.341us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 197.243us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 197.243us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 197.243us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 197.243us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 7.000s 372.904us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 848.033us 1 1 100.00
aes_tl_intg_err 2.000s 190.775us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 190.775us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 552.422us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 197.243us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 197.243us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 84.009us 1 1 100.00
aes_stress 3.000s 69.528us 1 1 100.00
aes_alert_reset 4.000s 552.422us 1 1 100.00
aes_core_fi 21.000s 10018.521us 0 1 0.00
sec_cm_gcm_config_sparse 2 3 66.67
aes_config_error 2.000s 90.569us 1 1 100.00
aes_stress 3.000s 69.528us 1 1 100.00
aes_core_fi 21.000s 10018.521us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 197.243us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 80.719us 1 1 100.00
aes_stress 3.000s 69.528us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 69.528us 1 1 100.00
aes_sideload 3.000s 95.544us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 80.719us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 80.719us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 80.719us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 80.719us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 80.719us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 69.528us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 69.528us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 563.883us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3.000s 563.883us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.341us 1 1 100.00
aes_ctr_fi 2.000s 78.067us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 563.883us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3.000s 563.883us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.341us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 55.341us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 563.883us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 3.000s 563.883us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 78.067us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 563.883us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3.000s 563.883us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.341us 1 1 100.00
aes_ctr_fi 2.000s 78.067us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 552.422us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3.000s 563.883us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.341us 1 1 100.00
aes_ctr_fi 2.000s 78.067us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3.000s 563.883us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.341us 1 1 100.00
aes_ctr_fi 2.000s 78.067us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 3.000s 563.883us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 78.067us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 563.883us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3.000s 563.883us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 55.341us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 14.000s 1509.186us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
aes_control_fi 30043419354177419365169293586213937329571005290844619631515171476115364924488 None
aes_stress_all 78616554026875158481269287403508958622469222625326378746342491249797933690577 None
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 112648679460119114252798187257973137876037028874266641528139960559367548445062 15737
UVM_INFO @ 1807100570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 6038161522160184785065408819306364118223830340082951583107870294107497352204 7076
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 38116187045533640076890992540788497874186813029014469714288556862287263064997 151
UVM_INFO @ 10018520897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 25040626642434220424173010593895835958501075434096284770538043947731161324420 353
UVM_INFO @ 1509186053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---