Simulation Results: clkmgr

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.95 %
  • code
  • 68.27 %
  • assert
  • 88.84 %
  • func
  • 70.73 %
  • line
  • 81.61 %
  • branch
  • 86.53 %
  • cond
  • 76.96 %
  • toggle
  • 96.23 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.430s 97.838us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.990s 26.139us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.700s 5.700us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 5.250s 441.771us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 1.270s 32.715us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.450s 42.216us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.700s 5.700us 0 1 0.00
clkmgr_csr_aliasing 1.270s 32.715us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 2.240s 183.838us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.000s 22.757us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.890s 26.898us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.430s 97.838us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.690s 8.682us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.710s 2.516us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.690s 8.682us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.770s 20.583us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.850s 16.938us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.800s 210.561us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.800s 210.561us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.990s 26.139us 1 1 100.00
clkmgr_csr_rw 0.700s 5.700us 0 1 0.00
clkmgr_csr_aliasing 1.270s 32.715us 0 1 0.00
clkmgr_same_csr_outstanding 0.720s 8.743us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.990s 26.139us 1 1 100.00
clkmgr_csr_rw 0.700s 5.700us 0 1 0.00
clkmgr_csr_aliasing 1.270s 32.715us 0 1 0.00
clkmgr_same_csr_outstanding 0.720s 8.743us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 92.250s 10039.551us 0 1 0.00
clkmgr_tl_intg_err 0.820s 8.162us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.370s 72.954us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.370s 72.954us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.370s 72.954us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.370s 72.954us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.660s 10.591us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.820s 8.162us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.690s 8.682us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.710s 2.516us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.370s 72.954us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 2.250s 167.739us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.700s 5.700us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 92.250s 10039.551us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.700s 5.700us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.700s 5.700us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 92.250s 10039.551us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.850s 4.771us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 3.160s 139.192us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency 112861980422158006099815689418344003673515930226407557356284736371225284907616 75
UVM_INFO @ 8681831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 98751322712641363830451408162798121931527787025354543932701526323877826278574 183
UVM_INFO @ 139191594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 107608200114129918924180705984647731581906397532129474995774997543433834159424 75
UVM_INFO @ 20582711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 115779256971780113311127048769092197304873040700165918753893707847497208253889 75
UVM_INFO @ 10590595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 54858644400462036733729302486889049048650225956051776300026263931795171885428 89
UVM_INFO @ 8162348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 52928508553746550186138755274765707217604502582732975577070952600916542776012 76
UVM_INFO @ 42216434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_csr_rw 68710379010386863098317701265461107673456176278918957929416375455988766106017 75
UVM_INFO @ 5699621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 27036116592060648783344314381179686388870105454020410487056681357902557945646 75
UVM_INFO @ 32715286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency_timeout 40538396587689056949743515429878266812604346729383126038944741862565407165435 78
UVM_INFO @ 2516208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en 1 test run
clkmgr_regwen 112413222465673297765803083349657682324383990587525362758491704837159865959000 74
UVM_INFO @ 4770975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 43615314231523640030431598292512948488278920812512129479043537787536290238462 104
UVM_INFO @ 10039551450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 88057082037082905684736807484616233128688677510986315273307245981189853386478 75
UVM_INFO @ 441770686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 23576159922407546820466511737294947279683886132564887247999389326656405437170 75
UVM_INFO @ 8742759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---