Simulation Results: dma

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.27 %
  • code
  • 90.76 %
  • assert
  • 96.61 %
  • func
  • 62.44 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 281.278us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 303.357us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 1422.701us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 14.150us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 17.702us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 3714.768us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 85.604us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 41.874us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 17.702us 1 1 100.00
dma_csr_aliasing 3.000s 85.604us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 72.000s 18801.591us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 91.000s 18717.763us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 377.000s 39039.713us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 377.000s 39039.713us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 91.000s 18717.763us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 116.000s 11947.726us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 377.000s 39039.713us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 5.000s 902.007us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 230.000s 87637.325us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 21.159us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 17.253us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 106.090us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 106.090us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 14.150us 1 1 100.00
dma_csr_rw 1.000s 17.702us 1 1 100.00
dma_csr_aliasing 3.000s 85.604us 1 1 100.00
dma_same_csr_outstanding 2.000s 235.178us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 14.150us 1 1 100.00
dma_csr_rw 1.000s 17.702us 1 1 100.00
dma_csr_aliasing 3.000s 85.604us 1 1 100.00
dma_same_csr_outstanding 2.000s 235.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 14.000s 381.705us 1 1 100.00
dma_generic_stress 116.000s 11947.726us 1 1 100.00
dma_handshake_stress 377.000s 39039.713us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 365.698us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 4.000s 441.783us 1 1 100.00
dma_sec_cm 2.000s 16.769us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 76.000s 9747.568us 1 1 100.00
dma_longer_transfer 3.000s 467.812us 1 1 100.00
dma_stress_all_with_rand_reset 15.000s 997.226us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 54187663728130495989467290918231620077881882071005743231729757341645751095380 118
UVM_INFO @ 997226292ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---