Simulation Results: edn/edn0

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 80.04 %
  • code
  • 91.89 %
  • assert
  • 98.45 %
  • func
  • 49.79 %
  • block
  • 96.30 %
  • line
  • 98.20 %
  • branch
  • 91.78 %
  • toggle
  • 82.24 %
  • FSM
  • 95.35 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 28.576us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 23.994us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 16.879us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.000s 47.436us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 154.510us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 75.849us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 16.879us 1 1 100.00
edn_csr_aliasing 2.000s 154.510us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 44.801us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 44.801us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 44.801us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 25.104us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 114.205us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 43.555us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 37.017us 1 1 100.00
edn_disable_auto_req_mode 1.000s 60.115us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 6.000s 296.570us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 13.612us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 30.710us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 120.386us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 120.386us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 23.994us 1 1 100.00
edn_csr_rw 2.000s 16.879us 1 1 100.00
edn_csr_aliasing 2.000s 154.510us 1 1 100.00
edn_same_csr_outstanding 3.000s 32.254us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 23.994us 1 1 100.00
edn_csr_rw 2.000s 16.879us 1 1 100.00
edn_csr_aliasing 2.000s 154.510us 1 1 100.00
edn_same_csr_outstanding 3.000s 32.254us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 8.000s 3194.579us 1 1 100.00
edn_tl_intg_err 1.000s 278.661us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 17.901us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 114.205us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.000s 3194.579us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.000s 3194.579us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 8.000s 3194.579us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 8.000s 3194.579us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 114.205us 1 1 100.00
edn_sec_cm 8.000s 3194.579us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 114.205us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.000s 278.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 133.000s 11712.669us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 89925824415542182429987740823894729887775717836603108831114773535385991114432 230
UVM_INFO @ 11712668960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---