Simulation Results: edn/edn1

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.58 %
  • code
  • 80.04 %
  • assert
  • 96.61 %
  • func
  • 77.10 %
  • line
  • 97.95 %
  • branch
  • 91.56 %
  • cond
  • 85.31 %
  • toggle
  • 85.62 %
  • FSM
  • 39.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 19.554us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.780s 25.574us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 42.189us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.530s 2785.367us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.140s 21.084us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.970s 129.006us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 42.189us 1 1 100.00
edn_csr_aliasing 1.140s 21.084us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.060s 33.937us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.060s 33.937us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.060s 33.937us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.990s 42.731us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.280s 158.012us 1 1 100.00
errs 1 1 100.00
edn_err 0.810s 29.771us 1 1 100.00
disable 2 2 100.00
edn_disable 0.800s 73.691us 1 1 100.00
edn_disable_auto_req_mode 0.800s 90.946us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.320s 414.636us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 22.892us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.900s 111.299us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.670s 148.454us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.670s 148.454us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.780s 25.574us 1 1 100.00
edn_csr_rw 0.770s 42.189us 1 1 100.00
edn_csr_aliasing 1.140s 21.084us 1 1 100.00
edn_same_csr_outstanding 1.190s 84.818us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.780s 25.574us 1 1 100.00
edn_csr_rw 0.770s 42.189us 1 1 100.00
edn_csr_aliasing 1.140s 21.084us 1 1 100.00
edn_same_csr_outstanding 1.190s 84.818us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
edn_sec_cm 3.690s 899.780us 0 1 0.00
edn_tl_intg_err 1.930s 396.484us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.930s 44.624us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.280s 158.012us 1 1 100.00
sec_cm_main_sm_fsm_sparse 0 1 0.00
edn_sec_cm 3.690s 899.780us 0 1 0.00
sec_cm_ack_sm_fsm_sparse 0 1 0.00
edn_sec_cm 3.690s 899.780us 0 1 0.00
sec_cm_fifo_ctr_redun 0 1 0.00
edn_sec_cm 3.690s 899.780us 0 1 0.00
sec_cm_ctr_redun 0 1 0.00
edn_sec_cm 3.690s 899.780us 0 1 0.00
sec_cm_main_sm_ctr_local_esc 1 2 50.00
edn_alert 1.280s 158.012us 1 1 100.00
edn_sec_cm 3.690s 899.780us 0 1 0.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.280s 158.012us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.930s 396.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 5.620s 293.367us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 105638901695044019119982941495999535723958819953170095192242817788397275368577 129
UVM_INFO @ 293367323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_receiver_driver.sv:262) driver [driver] m_transaction_tasks nonempty after reset: '{*:*} 1 test run
edn_sec_cm 40082055496055462901094590730958476517758280818735903778092403844708136063749 416
UVM_INFO @ 899780256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---