Simulation Results: entropy_src/rng_16bits

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 70.19 %
  • code
  • 82.78 %
  • assert
  • 73.64 %
  • func
  • 54.15 %
  • block
  • 94.12 %
  • line
  • 97.80 %
  • branch
  • 86.11 %
  • toggle
  • 52.43 %
  • FSM
  • 94.79 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 168.000us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 31.071us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 87.641us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 14.000s 802.654us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 1244.698us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 10.279us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 87.641us 1 1 100.00
entropy_src_csr_aliasing 3.000s 1244.698us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 168.000us 1 1 100.00
entropy_src_rng 340.000s 13056.239us 1 1 100.00
entropy_src_fw_ov 74.000s 13153.929us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 74.000s 13153.929us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 340.000s 13056.239us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 215.000s 14206.939us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 340.000s 13056.239us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 340.000s 13056.239us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 340.000s 13056.239us 1 1 100.00
entropy_src_intr 3.000s 40.354us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 340.000s 13056.239us 1 1 100.00
entropy_src_functional_alerts 5.000s 326.919us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 2.000s 222.228us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 31.239us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 7.000s 323.198us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 25.898us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 22.423us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 99.186us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 99.186us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 31.071us 1 1 100.00
entropy_src_csr_rw 2.000s 87.641us 1 1 100.00
entropy_src_csr_aliasing 3.000s 1244.698us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 164.215us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 31.071us 1 1 100.00
entropy_src_csr_rw 2.000s 87.641us 1 1 100.00
entropy_src_csr_aliasing 3.000s 1244.698us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 164.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 60.873us 1 1 100.00
entropy_src_tl_intg_err 2.000s 365.615us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 340.000s 13056.239us 1 1 100.00
entropy_src_cfg_regwen 2.000s 38.181us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 340.000s 13056.239us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 340.000s 13056.239us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 340.000s 13056.239us 1 1 100.00
entropy_src_fw_ov 74.000s 13153.929us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 31.239us 1 1 100.00
entropy_src_sec_cm 3.000s 60.873us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 31.239us 1 1 100.00
entropy_src_sec_cm 3.000s 60.873us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 340.000s 13056.239us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 31.239us 1 1 100.00
entropy_src_sec_cm 3.000s 60.873us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 31.239us 1 1 100.00
entropy_src_sec_cm 3.000s 60.873us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 31.239us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 326.919us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 2.000s 365.615us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 34.000s 14191.599us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 6.000s 976.679us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 59092423147886088241310479920936629847772842243523277247560946955400864567468 166
UVM_INFO @ 976678802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 75997470850157802960301034109384940693550707971935375419971340279466018492786 113
UVM_INFO @ 10278730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---