Simulation Results: hmac

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.47 %
  • code
  • 95.95 %
  • assert
  • 97.17 %
  • func
  • 30.28 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 12.000s 937.079us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 13.419us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 138.695us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.000s 4654.051us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 121.846us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 60.397us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 138.695us 1 1 100.00
hmac_csr_aliasing 3.000s 121.846us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 35.000s 4022.772us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 28.000s 852.034us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 12.000s 229.673us 1 1 100.00
hmac_test_sha384_vectors 23.000s 4229.887us 1 1 100.00
hmac_test_sha512_vectors 463.000s 100654.696us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 1878.122us 1 1 100.00
hmac_test_hmac384_vectors 20.000s 543.384us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 6713.867us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 9.000s 245.357us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 108.000s 13127.527us 1 1 100.00
error 1 1 100.00
hmac_error 56.000s 5844.077us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 121.000s 55476.857us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 12.000s 937.079us 1 1 100.00
hmac_long_msg 35.000s 4022.772us 1 1 100.00
hmac_back_pressure 28.000s 852.034us 1 1 100.00
hmac_datapath_stress 108.000s 13127.527us 1 1 100.00
hmac_burst_wr 9.000s 245.357us 1 1 100.00
hmac_stress_all 8.000s 1012.221us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 12.000s 937.079us 1 1 100.00
hmac_long_msg 35.000s 4022.772us 1 1 100.00
hmac_back_pressure 28.000s 852.034us 1 1 100.00
hmac_datapath_stress 108.000s 13127.527us 1 1 100.00
hmac_wipe_secret 121.000s 55476.857us 1 1 100.00
hmac_test_sha256_vectors 12.000s 229.673us 1 1 100.00
hmac_test_sha384_vectors 23.000s 4229.887us 1 1 100.00
hmac_test_sha512_vectors 463.000s 100654.696us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 1878.122us 1 1 100.00
hmac_test_hmac384_vectors 20.000s 543.384us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 6713.867us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 12.000s 937.079us 1 1 100.00
hmac_long_msg 35.000s 4022.772us 1 1 100.00
hmac_back_pressure 28.000s 852.034us 1 1 100.00
hmac_datapath_stress 108.000s 13127.527us 1 1 100.00
hmac_burst_wr 9.000s 245.357us 1 1 100.00
hmac_error 56.000s 5844.077us 1 1 100.00
hmac_wipe_secret 121.000s 55476.857us 1 1 100.00
hmac_test_sha256_vectors 12.000s 229.673us 1 1 100.00
hmac_test_sha384_vectors 23.000s 4229.887us 1 1 100.00
hmac_test_sha512_vectors 463.000s 100654.696us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 1878.122us 1 1 100.00
hmac_test_hmac384_vectors 20.000s 543.384us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 6713.867us 1 1 100.00
hmac_stress_all 8.000s 1012.221us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 8.000s 1012.221us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 74.992us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 22.274us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 42.530us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 42.530us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 13.419us 1 1 100.00
hmac_csr_rw 2.000s 138.695us 1 1 100.00
hmac_csr_aliasing 3.000s 121.846us 1 1 100.00
hmac_same_csr_outstanding 2.000s 179.380us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 13.419us 1 1 100.00
hmac_csr_rw 2.000s 138.695us 1 1 100.00
hmac_csr_aliasing 3.000s 121.846us 1 1 100.00
hmac_same_csr_outstanding 2.000s 179.380us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 69.345us 1 1 100.00
hmac_tl_intg_err 2.000s 357.236us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 357.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 12.000s 937.079us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 63.908us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 123.000s 36452.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 38.645us 1 1 100.00