Simulation Results

Simulation Results: i2c

29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.14 %

code
86.39 %

assert
97.46 %

func
80.56 %

block
96.17 %

line
95.56 %

branch
93.14 %

toggle
72.68 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		78.05%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	29.000s	3875.059us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	10.000s	540.337us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	28.834us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	10.000s	6320.151us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	643.434us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	198.707us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	117.219us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	10.000s	6320.151us	1	1	100.00
	i2c_csr_aliasing	2.000s	198.707us	1	1	100.00

32/41 passed

78.05 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	57.544us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3600.000s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	35.000s	2850.604us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	46.287us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3601.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	325.000s	6110.884us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	122.530us	1	1	100.00
	i2c_host_fifo_fmt_empty	5.000s	709.663us	1	1	100.00
	i2c_host_fifo_reset_rx	6.000s	975.102us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	1021.000s	4773.258us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	11.000s	661.418us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.000s	24.812us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	499.646us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.000s	1335.037us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	9.000s	762.637us	1	1	100.00
	i2c_target_intr_smoke	9.000s	10763.970us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	3.000s	377.841us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	167.326us	1	1	100.00
target_fifo_full				1	3	33.33
	i2c_target_stress_wr	3601.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	9.000s	762.637us	1	1	100.00
	i2c_target_intr_stress_wr	3600.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	9.000s	2880.523us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	61.000s	3013.180us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	7.000s	2667.112us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	4.000s	14724.134us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	282.112us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	184.671us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	35.000s	2850.604us	1	1	100.00
	i2c_host_perf_precise	2.000s	43.437us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	11.000s	661.418us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	310.438us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	1349.519us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.000s	887.602us	1	1	100.00
	i2c_target_nack_txstretch	2.000s	138.729us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	8.000s	318.483us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	486.896us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	47.407us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	19.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	493.551us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	493.551us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	28.834us	1	1	100.00
	i2c_csr_rw	10.000s	6320.151us	1	1	100.00
	i2c_csr_aliasing	2.000s	198.707us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	103.614us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	28.834us	1	1	100.00
	i2c_csr_rw	10.000s	6320.151us	1	1	100.00
	i2c_csr_aliasing	2.000s	198.707us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	103.614us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	53.429us	1	1	100.00
	i2c_sec_cm	2.000s	125.863us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	53.429us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	8.000s	520.109us	1
target_error_intr				1
	i2c_target_unexp_stop	1.000s	29.078us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	20.000s	3254.314us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				5 test runs
	i2c_host_fifo_watermark	50699024036149738467267049001623340980046806705403705642549640462437101020992	None
	i2c_host_stress_all	2406745405980082911833188208750429679620861906569205052150981824493124012661	None
	i2c_target_stress_wr	114422459742171935184698400911549756630733208748739714241765408694048625117601	None
	i2c_target_intr_stress_wr	64443202474871604905332579924934962043175373780168794452615457451221642968064	None
	i2c_target_stress_all	55353019604571230727472664164038172721716635686140170273949366223751910274639	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	63712135176794116798341487544310516214103276689109306480275520181088803631856	97	UVM_INFO @ 57543990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	63014938221224555510737031787560262272001288080828905995818146020311395272852	90	UVM_INFO @ 24811542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	112262004164597555413243924827609946516338220053392633234568753106532043685937	118	UVM_INFO @ 520108609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	21053908363140196833035471863571239268574543350289436419570857715040498802339	106	UVM_INFO @ 3254314431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	80362501137163913819904269888200757853696017653407778469894615409146185463427	93	UVM_INFO @ 499645950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	75329788954783382716832270514687295574349257588820269208559138847473865303820	87	UVM_INFO @ 29077673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	13140394725633270354121688525085270773028675500408746860349644963241016613568	88	UVM_INFO @ 14724134416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---