Simulation Results: lc_ctrl/volatile_unlock_disabled

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.82 %
  • code
  • 93.05 %
  • assert
  • 95.97 %
  • func
  • 86.45 %
  • block
  • 96.61 %
  • line
  • 97.29 %
  • branch
  • 91.38 %
  • toggle
  • 88.30 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 27.001us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 49.664us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 21.699us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 58.567us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 223.042us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 28.142us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 21.699us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 223.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 409.946us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 466.219us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 14.339us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 308.973us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 827.920us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 1311.582us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 827.920us 1 1 100.00
lc_ctrl_prog_failure 3.000s 308.973us 1 1 100.00
lc_ctrl_errors 5.000s 1311.582us 1 1 100.00
lc_ctrl_security_escalation 4.000s 289.161us 1 1 100.00
lc_ctrl_jtag_state_failure 14.000s 1663.228us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 1601.020us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 2710.107us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 150.995us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1245.754us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 1601.020us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 2710.107us 1 1 100.00
lc_ctrl_jtag_access 8.000s 923.847us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 943.492us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 916.766us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 195.520us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 2925.002us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 1969.572us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 212.819us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 328.031us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 206.730us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 602.436us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 123.468us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 37.000s 8977.392us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 24.692us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 204.701us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 204.701us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 49.664us 1 1 100.00
lc_ctrl_csr_rw 1.000s 21.699us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 223.042us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 51.325us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 49.664us 1 1 100.00
lc_ctrl_csr_rw 1.000s 21.699us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 223.042us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 51.325us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 129.458us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 503.853us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 503.853us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 466.219us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 827.920us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.458us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 827.920us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.458us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 827.920us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.458us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 827.920us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.458us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 827.920us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.458us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 827.920us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.458us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 827.920us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.458us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 827.920us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.458us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 289.161us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 409.946us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1245.754us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 1051.165us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 1051.165us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 356.022us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 1807.803us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 1807.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 24.000s 5107.288us 1 1 100.00