Simulation Results: lc_ctrl/volatile_unlock_enabled

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.80 %
  • code
  • 93.20 %
  • assert
  • 96.40 %
  • func
  • 85.81 %
  • block
  • 97.11 %
  • line
  • 97.69 %
  • branch
  • 92.68 %
  • toggle
  • 87.19 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.000s 36.965us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 27.073us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 17.859us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 23.781us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 101.438us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 76.394us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 17.859us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 101.438us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 228.799us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 794.958us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 12.920us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 167.824us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 327.643us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 579.715us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 327.643us 1 1 100.00
lc_ctrl_prog_failure 2.000s 167.824us 1 1 100.00
lc_ctrl_errors 6.000s 579.715us 1 1 100.00
lc_ctrl_security_escalation 4.000s 194.742us 1 1 100.00
lc_ctrl_jtag_state_failure 15.000s 3866.049us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 1900.310us 1 1 100.00
lc_ctrl_jtag_errors 11.000s 2779.754us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.000s 714.059us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 654.990us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 1900.310us 1 1 100.00
lc_ctrl_jtag_errors 11.000s 2779.754us 1 1 100.00
lc_ctrl_jtag_access 6.000s 1074.289us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.000s 3318.320us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 50.810us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 590.842us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 1802.834us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 1030.169us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 52.114us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 56.172us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 68.057us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 467.880us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 42.173us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 29.000s 15937.071us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 56.712us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.000s 97.392us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.000s 97.392us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 27.073us 1 1 100.00
lc_ctrl_csr_rw 1.000s 17.859us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 101.438us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 59.428us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 27.073us 1 1 100.00
lc_ctrl_csr_rw 1.000s 17.859us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 101.438us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 59.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 535.855us 1 1 100.00
lc_ctrl_tl_intg_err 1.000s 143.215us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.000s 143.215us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 794.958us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 327.643us 1 1 100.00
lc_ctrl_sec_cm 4.000s 535.855us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 327.643us 1 1 100.00
lc_ctrl_sec_cm 4.000s 535.855us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 327.643us 1 1 100.00
lc_ctrl_sec_cm 4.000s 535.855us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 327.643us 1 1 100.00
lc_ctrl_sec_cm 4.000s 535.855us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 327.643us 1 1 100.00
lc_ctrl_sec_cm 4.000s 535.855us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 327.643us 1 1 100.00
lc_ctrl_sec_cm 4.000s 535.855us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 327.643us 1 1 100.00
lc_ctrl_sec_cm 4.000s 535.855us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 327.643us 1 1 100.00
lc_ctrl_sec_cm 4.000s 535.855us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 194.742us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 228.799us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 654.990us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 320.057us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 320.057us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 299.172us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 266.404us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 266.404us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 46.000s 14310.989us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 94543434411201214124718508848423242164111360514725146895901851012356295149669 3170
UVM_INFO @ 14310989048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---