| V1 |
|
83.33% |
| V2 |
|
72.73% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 60.000s | 27343.278us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 14.545us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 1.000s | 52.419us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 3.000s | 670.130us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 1.000s | 14.799us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 1.000s | 1.530us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 1.000s | 52.419us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 14.799us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 0 | 1 | 0.00 | |||
| mbx_stress | 4.000s | 466.431us | 0 | 1 | 0.00 | |
| mbx_max_activity | 1 | 1 | 100.00 | |||
| mbx_stress_zero_delays | 24.000s | 1446.831us | 1 | 1 | 100.00 | |
| mbx_imbx_oob | 0 | 1 | 0.00 | |||
| mbx_imbx_oob | 2.000s | 118.228us | 0 | 1 | 0.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 9.000s | 1418.704us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 1.000s | 36.463us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 2.000s | 54.173us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 1.000s | 4.512us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 1.000s | 4.512us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 14.545us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 52.419us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 14.799us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 1.000s | 21.509us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 14.545us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 52.419us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 14.799us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 1.000s | 21.509us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_tl_intg_err | 2.000s | 292.694us | 1 | 1 | 100.00 | |
| mbx_sec_cm | 1.000s | 111.776us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). | 2 test runs | |||
| mbx_tl_errors | 12796229365874493961099321796731474867374345988412283828272384962216744214997 | 85 |
TL item was: req: (cip_tl_seq_item@18814) { a_addr: 'h9d5dfb4 a_data: 'hb44ca90c a_mask: 'hd a_size: 'h2 a_param: 'h0 a_source: 'h16 a_opcode: 'h1 a_user: 'h25960 d_param: 'h0 d_source: 'h16 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 4512391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| mbx_csr_mem_rw_with_rand_reset | 47535859577604247019255990271336063635567126726847951917247799117412145810391 | 86 |
TL item was: req: (cip_tl_seq_item@20777) { a_addr: 'h7f2ca54 a_data: 'hada46d03 a_mask: 'h3 a_size: 'h1 a_param: 'h0 a_source: 'h26 a_opcode: 'h0 a_user: 'h250b0 d_param: 'h0 d_source: 'h26 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 1530441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched | 1 test run | |||
| mbx_stress | 89862431216567980842497347885322057834237976279049603776121896051037835835952 | 269 |
UVM_INFO @ 466431483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register | 1 test run | |||
| mbx_imbx_oob | 37729479113207255901688550896821697640436436381983954575187700643775758855060 | 95 |
UVM_INFO @ 118228072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|