Simulation Results: otbn

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.53 %
  • code
  • 81.83 %
  • assert
  • 89.29 %
  • func
  • 97.46 %
  • block
  • 97.73 %
  • line
  • 97.93 %
  • branch
  • 81.84 %
  • toggle
  • 81.35 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 14.000s 45.988us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 21.157us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 28.934us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 19.468us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 336.474us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 59.858us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 68.078us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 19.468us 1 1 100.00
otbn_csr_aliasing 4.000s 59.858us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 123.000s 7239.287us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 36.000s 1990.021us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 24.000s 309.155us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 33.000s 295.575us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 43.000s 318.169us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 115.000s 1457.711us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 7.000s 18.042us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.838us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 94.285us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 73.162us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 55.085us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 47.822us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 47.822us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 28.934us 1 1 100.00
otbn_csr_rw 4.000s 19.468us 1 1 100.00
otbn_csr_aliasing 4.000s 59.858us 1 1 100.00
otbn_same_csr_outstanding 5.000s 29.322us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 28.934us 1 1 100.00
otbn_csr_rw 4.000s 19.468us 1 1 100.00
otbn_csr_aliasing 4.000s 59.858us 1 1 100.00
otbn_same_csr_outstanding 5.000s 29.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 11.000s 23.903us 1 1 100.00
otbn_dmem_err 9.000s 35.849us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 10.000s 217.126us 1 1 100.00
otbn_controller_ispr_rdata_err 8.000s 380.298us 0 1 0.00
otbn_mac_bignum_acc_err 15.000s 427.270us 1 1 100.00
otbn_urnd_err 5.000s 52.103us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 27.666us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 30.424us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 81.593us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
otbn_tl_intg_err 10.000s 259.036us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 23.000s 106.518us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 14.000s 45.988us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 9.000s 35.849us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 11.000s 23.903us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 259.036us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 18.042us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 23.903us 1 1 100.00
otbn_dmem_err 9.000s 35.849us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.838us 1 1 100.00
otbn_illegal_mem_acc 6.000s 27.666us 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 21.157us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 23.903us 1 1 100.00
otbn_dmem_err 9.000s 35.849us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.838us 1 1 100.00
otbn_illegal_mem_acc 6.000s 27.666us 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 18.042us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 23.903us 1 1 100.00
otbn_dmem_err 9.000s 35.849us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.838us 1 1 100.00
otbn_illegal_mem_acc 6.000s 27.666us 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 21.157us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 14.050us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 13.991us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 27.000s 734.046us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 27.000s 734.046us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 21.316us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 63.143us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 44.240us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 44.240us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 10.675us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 21.157us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 21.157us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 21.157us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 43.000s 318.169us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 21.157us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 21.157us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 93.000s 721.334us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 21.157us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 573.000s 3173.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 8.000s 43.967us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 31.990us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_controller_ispr_rdata_err 33544607973616406945588853033344805607382190710518565618714168097090985686367 109
UVM_INFO @ 380297801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 40236130003322847876343015768057019448994376592182835225749757506834603242414 147
UVM_INFO @ 43966669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 103766715414537666291354077825613326765116455593912356085571725024814220625704 310
UVM_INFO @ 295574786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---