Simulation Results: otp_ctrl

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.28 %
  • code
  • 72.47 %
  • assert
  • 93.85 %
  • func
  • 56.53 %
  • line
  • 87.52 %
  • branch
  • 84.17 %
  • cond
  • 85.83 %
  • toggle
  • 66.14 %
  • FSM
  • 38.70 %
Validation stages
V1
100.00%
V2
80.00%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.590s 106.679us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 9.860s 1070.537us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.170s 1710.271us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.630s 95.023us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.990s 1177.031us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.860s 1316.883us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.620s 140.185us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.630s 95.023us 1 1 100.00
otp_ctrl_csr_aliasing 4.860s 1316.883us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.950s 44.847us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.910s 141.238us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 115.410s 17471.950us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.270s 433.127us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 3.760s 291.755us 0 1 0.00
otp_ctrl_check_fail 8.130s 2171.097us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.510s 163.073us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 17.580s 4602.610us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 15.670s 5187.005us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 5.380s 208.056us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 35.520s 3833.984us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.220s 293.703us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 4.730s 275.043us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 8.940s 6584.983us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.090s 718.462us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.400s 150.354us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.510s 119.140us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.510s 119.140us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.170s 1710.271us 1 1 100.00
otp_ctrl_csr_rw 1.630s 95.023us 1 1 100.00
otp_ctrl_csr_aliasing 4.860s 1316.883us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.060s 855.789us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.170s 1710.271us 1 1 100.00
otp_ctrl_csr_rw 1.630s 95.023us 1 1 100.00
otp_ctrl_csr_aliasing 4.860s 1316.883us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.060s 855.789us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
otp_ctrl_tl_intg_err 22.440s 4461.539us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 22.440s 4461.539us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 9.860s 1070.537us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 9.860s 1070.537us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
otp_ctrl_macro_errs 2.220s 293.703us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
otp_ctrl_macro_errs 2.220s 293.703us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.340s 250.592us 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.270s 433.127us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 8.130s 2171.097us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 17.580s 4602.610us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 17.580s 4602.610us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 17.580s 4602.610us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 17.580s 4602.610us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 17.580s 4602.610us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 9.860s 1070.537us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 17.580s 4602.610us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 9.860s 1070.537us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.120s 31476.772us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.510s 163.073us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 9.860s 1070.537us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 9.860s 1070.537us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.220s 293.703us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 128.200s 68904.048us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.480s 31.703us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 109940505517589662001807901813018704642710085514679393222323306593350999660891 110283
UVM_INFO @ 17471950370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 61550013986084003292241512411045947468433467414367585191603721876686317723833 89
UVM_INFO @ 68904048089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 1 test run
otp_ctrl_background_chks 100577858540755569080408868118744373426073517656311738543851302311020490406913 3580
UVM_INFO @ 291754605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 26301649352717942090126779211299341456723622673522457890938070046775752897787 450
UVM_INFO @ 293703446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 80083909391775402525236703435854612512651232195680331482526171026507659277064 91
UVM_INFO @ 31703047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all 98853112658179182779193673174271782845147990891704487732385825848798905177896 3020
UVM_INFO @ 6584982917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---