Simulation Results: rom_ctrl/64kb

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.92 %
  • code
  • 84.82 %
  • assert
  • 96.80 %
  • func
  • 97.15 %
  • block
  • 87.31 %
  • line
  • 86.51 %
  • branch
  • 87.12 %
  • toggle
  • 84.69 %
  • FSM
  • 80.95 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 746.169us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 57.784us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 60.213us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 132.764us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 107.971us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 126.395us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 60.213us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 107.971us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 88.343us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 55.785us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.000s 328.187us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 11.000s 2058.415us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 70.651us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 56.628us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 709.808us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 709.808us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 57.784us 1 1 100.00
rom_ctrl_csr_rw 3.000s 60.213us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 107.971us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 72.210us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 57.784us 1 1 100.00
rom_ctrl_csr_rw 3.000s 60.213us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 107.971us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 72.210us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 17.000s 2791.870us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 437.973us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 195.000s 1688.392us 1 1 100.00
rom_ctrl_tl_intg_err 41.000s 1674.493us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 195.000s 1688.392us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 195.000s 1688.392us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 17.000s 2791.870us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 17.000s 2791.870us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 17.000s 2791.870us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 17.000s 2791.870us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 17.000s 2791.870us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 195.000s 1688.392us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 195.000s 1688.392us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 746.169us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 746.169us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 746.169us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 41.000s 1674.493us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 17.000s 2791.870us 0 1 0.00
rom_ctrl_kmac_err_chk 3.000s 70.651us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 17.000s 2791.870us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 17.000s 2791.870us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 17.000s 2791.870us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 437.973us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 195.000s 1688.392us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 22.000s 2334.181us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 22989045251289330707917967953905513196945820059676314520453476742253682521205 88
UVM_INFO @ 328186591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1049) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] Expected alert (fatal) did not fire in * cycles. 1 test run
rom_ctrl_corrupt_sig_fatal_chk 46543584243790669462754456906773506774530773321954047927255198225236262740915 94
UVM_INFO @ 2791870467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---