Simulation Results

Simulation Results: rv_dm/use_dmi_interface

29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.56 %

code
74.98 %

assert
95.50 %

func
92.19 %

block
89.63 %

line
89.47 %

branch
71.87 %

toggle
76.10 %

FSM
62.50 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	32.000s	858.169us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	35.000s	1108.190us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	30.000s	172.157us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	54.000s	43133.407us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	30.000s	330.846us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	36.000s	1552.181us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	33.000s	3088.820us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	40.000s	7828.121us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	59.000s	65971.759us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	617.820us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	32.000s	809.520us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	33.000s	389.254us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	36.000s	288.747us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	33.000s	93.092us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	31.000s	355.717us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	31.000s	234.032us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	30.000s	294.923us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	617.820us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	34.000s	597.091us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	30.000s	222.895us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	33.000s	389.254us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	30.000s	68.274us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	32.000s	81.848us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	30.000s	356.025us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	75.000s	90777.879us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	60.000s	4135.831us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	30.000s	118.424us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	60.000s	4135.831us	1	1	100.00
	rv_dm_csr_rw	30.000s	356.025us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	29.000s	124.817us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	31.000s	137.639us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	32.000s	858.169us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	30.000s	262.391us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	31.000s	118.197us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	34.000s	383.898us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	32.000s	2466.568us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	33.000s	4277.431us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	32.000s	1992.682us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	32.000s	143.570us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	31.000s	309.645us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	29.000s	182.858us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	33.000s	1739.218us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	30.000s	230.858us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	33.000s	85.765us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	37.000s	3563.746us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	88.000s	8550.708us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	31.000s	76.713us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	29.000s	1536.115us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	30.000s	37.603us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	983.678us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	983.678us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	60.000s	4135.831us	1	1	100.00
	rv_dm_csr_hw_reset	32.000s	81.848us	1	1	100.00
	rv_dm_csr_rw	30.000s	356.025us	1	1	100.00
	rv_dm_same_csr_outstanding	32.000s	288.116us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	60.000s	4135.831us	1	1	100.00
	rv_dm_csr_hw_reset	32.000s	81.848us	1	1	100.00
	rv_dm_csr_rw	30.000s	356.025us	1	1	100.00
	rv_dm_same_csr_outstanding	32.000s	288.116us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	32.000s	2647.244us	1	1	100.00
	rv_dm_tl_intg_err	34.000s	1176.713us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	34.000s	1176.713us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	33.000s	1739.218us	1	1	100.00
	rv_dm_debug_disabled	29.000s	47.855us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	33.000s	1739.218us	1	1	100.00
	rv_dm_debug_disabled	29.000s	47.855us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	32.000s	858.169us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	32.000s	326.610us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	29.000s	111.847us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	29.000s	111.847us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	32.000s	326.610us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	38.000s	557.385us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	516.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	100837798491626091953789740847555987338570202087059062290558918482902903925666	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23816
	rv_dm_delayed_resp_sba_tl_access	23997518208591402596166977996769626168346991250601336121741426618556890867884	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23820
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_bad_sba_tl_access	75775963216709579161494368599593087599011505375658903506707158979977882012637	107	UVM_INFO @ 143570127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	79898633238490315001769766684538056722345576804426606246735253930183131722402	107	UVM_INFO @ 309645443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	42146982214609090040486341707432674173682755888092556821424154612039293941686	87	UVM_INFO @ 288746712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	28732307064399461952362607395621230764454363754738084368892537289990701495510	94	UVM_INFO @ 557385150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	44567038391756251203669573784833595269103986341227585881368064501582254734641	87	UVM_INFO @ 85764602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	44001260196786013885565608872318148832099476127215415063224158383299975825962	91	UVM_INFO @ 1536115187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	37716290006891423945467782247267035245498773958829198928804254842371541134157	87	UVM_INFO @ 182858323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	31806547332185367605885400838328875535102414045826407256641195720376314065223	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---