Simulation Results: rv_timer

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.71 %
  • code
  • 95.77 %
  • assert
  • 97.78 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.04 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 70.548us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 33.785us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 12.693us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 312.979us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 35.423us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 79.546us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 12.693us 1 1 100.00
rv_timer_csr_aliasing 2.000s 35.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 135.600us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 339.426us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 1.000s 69.638us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 1.000s 69.638us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.000s 5565.325us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 51.274us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 15.617us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 247.043us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 247.043us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 33.785us 1 1 100.00
rv_timer_csr_rw 1.000s 12.693us 1 1 100.00
rv_timer_csr_aliasing 2.000s 35.423us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 20.141us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 33.785us 1 1 100.00
rv_timer_csr_rw 1.000s 12.693us 1 1 100.00
rv_timer_csr_aliasing 2.000s 35.423us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 20.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 243.303us 1 1 100.00
rv_timer_tl_intg_err 2.000s 129.768us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 129.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.000s 81.152us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 50.352us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 24.000s 18713.805us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 14792122184881797921317776327407043877395444181909984040744213346563861053870 85
UVM_INFO @ 81151824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 98474450711960780317223963890571501665602938810551585315519766922599111614084 84
UVM_INFO @ 135600137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 112467359492147404507700497803495221716632780959060162520104015924163825977304 84
UVM_INFO @ 50352320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---