Simulation Results: spi_device/1r1w

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.56 %
  • code
  • 89.51 %
  • assert
  • 95.40 %
  • func
  • 65.76 %
  • block
  • 98.33 %
  • line
  • 98.75 %
  • branch
  • 96.96 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 134.000s 13104.585us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 3.000s 50.589us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 379.691us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 36.000s 797.637us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 12.000s 2499.973us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 33.187us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 379.691us 1 1 100.00
spi_device_csr_aliasing 12.000s 2499.973us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 11.376us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 22.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 27.429us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 0.963us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 4.929us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.000s 143.774us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.000s 143.774us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 61.000s 9354.766us 1 1 100.00
spi_device_tpm_sts_read 2.000s 71.823us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 34.000s 1934.003us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 5.000s 140.958us 1 1 100.00
spi_device_flash_all 17.000s 1627.600us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 20.000s 8902.289us 1 1 100.00
spi_device_flash_all 17.000s 1627.600us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 20.000s 8902.289us 1 1 100.00
spi_device_flash_all 17.000s 1627.600us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 17.000s 1627.600us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.000s 244.846us 1 1 100.00
spi_device_flash_all 17.000s 1627.600us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.000s 244.846us 1 1 100.00
spi_device_flash_all 17.000s 1627.600us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.000s 244.846us 1 1 100.00
spi_device_flash_all 17.000s 1627.600us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.000s 244.846us 1 1 100.00
spi_device_flash_all 17.000s 1627.600us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.000s 244.846us 1 1 100.00
spi_device_flash_all 17.000s 1627.600us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.000s 594.726us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 14.000s 3225.337us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 14.000s 3225.337us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 14.000s 3225.337us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 7.000s 191.160us 1 1 100.00
spi_device_read_buffer_direct 10.000s 618.471us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 14.000s 3225.337us 1 1 100.00
spi_device_flash_all 17.000s 1627.600us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 17.000s 1627.600us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 17.000s 1627.600us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 70.433us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 70.433us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 48.000s 5641.139us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 134.000s 13104.585us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 73.000s 3836.615us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 77.000s 12416.058us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 51.740us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 42.239us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 136.311us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 136.311us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 3.000s 50.589us 1 1 100.00
spi_device_csr_rw 3.000s 379.691us 1 1 100.00
spi_device_csr_aliasing 12.000s 2499.973us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 537.332us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 3.000s 50.589us 1 1 100.00
spi_device_csr_rw 3.000s 379.691us 1 1 100.00
spi_device_csr_aliasing 12.000s 2499.973us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 537.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 88.855us 1 1 100.00
spi_device_tl_intg_err 9.000s 1239.319us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.000s 1239.319us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 8100024601220729527710320456933625620048122148564912549167537317773638896867 87
UVM_ERROR @ 836491 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[939] not found within the scope .
UVM_ERROR @ 836491 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[939] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 115515815745975246796664801388069656227813951118167066526015957824428446867306 85
UVM_ERROR @ 2365959 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x217 [1000010111] vs 0x0 [0])
UVM_ERROR @ 2443959 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x236 [1000110110] vs 0x0 [0])
UVM_ERROR @ 2538959 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x275 [1001110101] vs 0x0 [0])
UVM_ERROR @ 2588959 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2b6 [1010110110] vs 0x0 [0])