Simulation Results: spi_host

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.87 %
  • code
  • 91.14 %
  • assert
  • 96.22 %
  • func
  • 88.24 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 15.000s 2084.183us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 34.093us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 20.074us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 4040.893us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 34.257us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 251.756us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 20.074us 1 1 100.00
spi_host_csr_aliasing 2.000s 34.257us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 36.069us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 73.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 24.618us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 274.140us 1 1 100.00
spi_host_error_cmd 1.000s 55.908us 1 1 100.00
spi_host_event 16.000s 1869.851us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 4.000s 372.893us 1 1 100.00
speed 1 1 100.00
spi_host_speed 4.000s 372.893us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 4.000s 372.893us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 312.000s 32485.153us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 4.000s 71.168us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 119.129us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 4.000s 372.893us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 4.000s 372.893us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 15.000s 2084.183us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 15.000s 2084.183us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 16.000s 1482.366us 1 1 100.00
spien 1 1 100.00
spi_host_spien 30.000s 5341.307us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 788.000s 153334.402us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 1.000s 46.331us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 274.140us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 45.465us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 16.871us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 649.014us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 649.014us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 34.093us 1 1 100.00
spi_host_csr_rw 1.000s 20.074us 1 1 100.00
spi_host_csr_aliasing 2.000s 34.257us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 41.628us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 34.093us 1 1 100.00
spi_host_csr_rw 1.000s 20.074us 1 1 100.00
spi_host_csr_aliasing 2.000s 34.257us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 41.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 65.694us 1 1 100.00
spi_host_sec_cm 2.000s 252.041us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 65.694us 1 1 100.00