Simulation Results: sram_ctrl/main

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.68 %
  • code
  • 95.69 %
  • assert
  • 97.55 %
  • func
  • 93.80 %
  • block
  • 96.09 %
  • line
  • 96.75 %
  • branch
  • 94.16 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 374.041us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 55.439us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 39.450us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 38.500us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 49.629us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 370.215us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 39.450us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 49.629us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 223.000s 22466.284us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 53.000s 9233.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 18.000s 11284.268us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 136.000s 4171.326us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 152.000s 15325.273us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 27.000s 8198.137us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 9.000s 2813.069us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 28.000s 11949.134us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 2908.434us 1 1 100.00
sram_ctrl_partial_access_b2b 81.000s 13884.441us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 5.000s 664.742us 0 1 0.00
sram_ctrl_throughput_w_partial_write 6.000s 1321.432us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 1414.678us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 5.000s 1300.383us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 380.785us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 209.000s 96198.909us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 25.126us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 106.943us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 106.943us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 55.439us 1 1 100.00
sram_ctrl_csr_rw 2.000s 39.450us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 49.629us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 30.562us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 55.439us 1 1 100.00
sram_ctrl_csr_rw 2.000s 39.450us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 49.629us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 30.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 33.000s 70530.780us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 961.006us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 115.676us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 961.006us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 115.676us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 1300.383us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 1300.383us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 39.450us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 28.000s 11949.134us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 28.000s 11949.134us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 28.000s 11949.134us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 9.000s 2813.069us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 1451.647us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 33.000s 70530.780us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 696.282us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 374.041us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 374.041us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 28.000s 11949.134us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 961.006us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 9.000s 2813.069us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 961.006us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 961.006us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 374.041us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 961.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 28.000s 5924.178us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 39323286958437673279979496666474114603803487803821564558409056213945904471161 86
UVM_INFO @ 664741645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 53799694615358103685741519613205618576770386487912771921523943806234144645104 86
UVM_INFO @ 1321431950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 24749886338436248179383464315911919136877512300907736593626102702035766553326 86
UVM_INFO @ 1414677668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---