Simulation Results: uart

 
29/07/2026 19:40:36 DVSim: v1.50.0 sha: 89a1064 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.00 %
  • code
  • 92.73 %
  • assert
  • 98.56 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.000s 483.911us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 1076.349us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 47.833us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 529.831us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 33.551us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 61.855us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 47.833us 1 1 100.00
uart_csr_aliasing 1.000s 33.551us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 29.000s 33578.969us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.000s 483.911us 1 1 100.00
uart_tx_rx 29.000s 33578.969us 1 1 100.00
parity_error 2 2 100.00
uart_intr 26.000s 184497.928us 1 1 100.00
uart_rx_parity_err 133.000s 105634.455us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 29.000s 33578.969us 1 1 100.00
uart_intr 26.000s 184497.928us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 73.000s 78767.075us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 124.000s 74863.694us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 17.000s 22936.425us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 26.000s 184497.928us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 26.000s 184497.928us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 26.000s 184497.928us 1 1 100.00
perf 1 1 100.00
uart_perf 68.000s 12546.373us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 7.000s 8610.628us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 7.000s 8610.628us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.000s 318.539us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.000s 1784.092us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.000s 831.649us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 7.000s 5375.738us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 158.000s 102285.043us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 352.000s 360329.513us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 2.000s 10.602us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 15.403us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 3.000s 608.618us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 3.000s 608.618us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 1076.349us 1 1 100.00
uart_csr_rw 1.000s 47.833us 1 1 100.00
uart_csr_aliasing 1.000s 33.551us 1 1 100.00
uart_same_csr_outstanding 1.000s 22.380us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 1076.349us 1 1 100.00
uart_csr_rw 1.000s 47.833us 1 1 100.00
uart_csr_aliasing 1.000s 33.551us 1 1 100.00
uart_same_csr_outstanding 1.000s 22.380us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 2.000s 106.161us 1 1 100.00
uart_tl_intg_err 2.000s 93.173us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 93.173us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 38.000s 5917.214us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 22105232968947547181021202788789190304746984544951719289049842572539228217427 83
UVM_ERROR @ 166098670 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 166138670 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 283738670 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 283738670 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0