Simulation Results: ac_range_check

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.91 %
  • code
  • 93.09 %
  • assert
  • 97.75 %
  • func
  • 57.88 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.09 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 19.000s 778.181us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 29.000s 3524.422us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 65.286us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 38.952us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 22.000s 1410.045us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 13.000s 364.832us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 28.608us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 38.952us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 364.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 388.836us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 27.000s 1627.717us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 205.000s 11341.955us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 24.971us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 46.323us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 819.755us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 819.755us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 65.286us 1 1 100.00
ac_range_check_csr_rw 2.000s 38.952us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 364.832us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 304.538us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 65.286us 1 1 100.00
ac_range_check_csr_rw 2.000s 38.952us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 364.832us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 304.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 943.246us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 943.246us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 943.246us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 943.246us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 76.000s 17826.621us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 15.571us 1 1 100.00
ac_range_check_tl_intg_err 6.000s 371.808us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 234.000s 11883.499us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 17.000s 2278.468us 1 1 100.00