Simulation Results: alert_handler

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.26 %
  • code
  • 89.68 %
  • assert
  • 98.29 %
  • func
  • 76.82 %
  • line
  • 99.71 %
  • branch
  • 98.50 %
  • cond
  • 90.83 %
  • toggle
  • 85.18 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 10.790s 192.483us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.820s 488.535us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 7.640s 583.332us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 252.480s 24099.164us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 102.680s 2455.376us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.630s 106.489us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 7.640s 583.332us 1 1 100.00
alert_handler_csr_aliasing 102.680s 2455.376us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 95.180s 17957.134us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 55.830s 5824.326us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1708.790s 211821.201us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 5.190s 233.543us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 10.790s 192.483us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 54.200s 1476.671us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 22.170s 1031.188us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 271.620s 41727.029us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1336.390s 139945.293us 1 1 100.00
alert_handler_lpg_stub_clk 937.390s 12956.704us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 35.580s 978.437us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 5.860s 138.945us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.560s 25.752us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.380s 29.652us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 10.560s 714.681us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 10.560s 714.681us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.820s 488.535us 1 1 100.00
alert_handler_csr_rw 7.640s 583.332us 1 1 100.00
alert_handler_csr_aliasing 102.680s 2455.376us 1 1 100.00
alert_handler_same_csr_outstanding 38.470s 2993.691us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.820s 488.535us 1 1 100.00
alert_handler_csr_rw 7.640s 583.332us 1 1 100.00
alert_handler_csr_aliasing 102.680s 2455.376us 1 1 100.00
alert_handler_same_csr_outstanding 38.470s 2993.691us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 140.710s 2584.466us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 140.710s 2584.466us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 140.710s 2584.466us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 140.710s 2584.466us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 894.770s 33143.714us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 36.080s 1113.874us 1 1 100.00
alert_handler_tl_intg_err 32.720s 919.948us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 32.720s 919.948us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 140.710s 2584.466us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 10.790s 192.483us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 10.790s 192.483us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 10.790s 192.483us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 10.790s 192.483us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 5.190s 233.543us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1336.390s 139945.293us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 5.190s 233.543us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1708.790s 211821.201us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1708.790s 211821.201us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 36.080s 1113.874us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 36.080s 1113.874us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 36.080s 1113.874us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 36.080s 1113.874us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 36.080s 1113.874us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 36.080s 1113.874us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 36.080s 1113.874us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 36.080s 1113.874us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 36.080s 1113.874us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 11.050s 216.103us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 8708649724661475870976522672335305287764814831093943980088630532920992961111 202
UVM_INFO @ 138945291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 56551250656632335357357089486467776626384319807051671242066924573906478097772 84
UVM_INFO @ 216102675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---