| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| aon_timer_smoke | 1.000s | 603.456us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.000s | 960.614us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aon_timer_csr_rw | 2.000s | 313.357us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aon_timer_csr_bit_bash | 13.000s | 7163.666us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aon_timer_csr_aliasing | 2.000s | 603.073us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 1.000s | 518.852us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aon_timer_csr_rw | 2.000s | 313.357us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 2.000s | 603.073us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| aon_timer_mem_walk | 1.000s | 416.146us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| aon_timer_mem_partial_access | 2.000s | 405.827us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 1 | 1 | 100.00 | |||
| aon_timer_prescaler | 2.000s | 719.693us | 1 | 1 | 100.00 | |
| jump | 1 | 1 | 100.00 | |||
| aon_timer_jump | 2.000s | 678.431us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| aon_timer_stress_all | 20.000s | 41971.451us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aon_timer_alert_test | 2.000s | 421.860us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| aon_timer_intr_test | 1.000s | 493.680us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aon_timer_tl_errors | 2.000s | 497.925us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aon_timer_tl_errors | 2.000s | 497.925us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.000s | 960.614us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 2.000s | 313.357us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 2.000s | 603.073us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 3.000s | 2170.153us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.000s | 960.614us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 2.000s | 313.357us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 2.000s | 603.073us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 3.000s | 2170.153us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| aon_timer_sec_cm | 5.000s | 3802.408us | 1 | 1 | 100.00 | |
| aon_timer_tl_intg_err | 6.000s | 8481.000us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| aon_timer_tl_intg_err | 6.000s | 8481.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 1 | 1 | 100.00 | |||
| aon_timer_smoke_max_thold | 3.000s | 698.949us | 1 | 1 | 100.00 | |
| min_threshold | 1 | 1 | 100.00 | |||
| aon_timer_smoke_min_thold | 2.000s | 569.274us | 1 | 1 | 100.00 | |
| wkup_count_hi_cdc | 1 | 1 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 5.000s | 3103.956us | 1 | 1 | 100.00 | |
| custom_intr | 1 | 1 | 100.00 | |||
| aon_timer_custom_intr | 2.000s | 650.150us | 1 | 1 | 100.00 | |
| alternating_on_off | 1 | 1 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 3.000s | 3965.122us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 12.000s | 2631.074us | 1 | 1 | 100.00 | |