Simulation Results: clkmgr

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.81 %
  • code
  • 67.29 %
  • assert
  • 88.02 %
  • func
  • 66.12 %
  • line
  • 81.15 %
  • branch
  • 85.86 %
  • cond
  • 74.63 %
  • toggle
  • 94.81 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
53.85%
V2S
12.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 2.090s 184.379us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.440s 113.965us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.640s 3.681us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.600s 2.150us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.750s 3.851us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.530s 93.766us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.640s 3.681us 0 1 0.00
clkmgr_csr_aliasing 0.750s 3.851us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.830s 25.591us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 2.040s 142.604us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.880s 34.627us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 2.090s 184.379us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.710s 7.849us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.660s 1.843us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.710s 7.849us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.830s 14.588us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.270s 36.357us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.420s 199.041us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.420s 199.041us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.440s 113.965us 1 1 100.00
clkmgr_csr_rw 0.640s 3.681us 0 1 0.00
clkmgr_csr_aliasing 0.750s 3.851us 0 1 0.00
clkmgr_same_csr_outstanding 0.720s 7.187us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.440s 113.965us 1 1 100.00
clkmgr_csr_rw 0.640s 3.681us 0 1 0.00
clkmgr_csr_aliasing 0.750s 3.851us 0 1 0.00
clkmgr_same_csr_outstanding 0.720s 7.187us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.840s 16.362us 0 1 0.00
clkmgr_tl_intg_err 0.690s 8.640us 0 1 0.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 1625.040s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 1625.040s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 1625.040s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 1625.040s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.620s 2.023us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.690s 8.640us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.710s 7.849us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.660s 1.843us 0 1 0.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 1625.040s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.230s 69.509us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.640s 3.681us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.840s 16.362us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.640s 3.681us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.640s 3.681us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.840s 16.362us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.640s 4.205us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.750s 5.128us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency_timeout 700275401064288190963594509171186404432214467806355625996504874496488958132 78
UVM_INFO @ 1842878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 88218713481243346607392464858647082489886823619174459723462582777667007802884 79
UVM_INFO @ 5127829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 32049091995704100015424380209219423937457069581510513172176697881493192142749 78
UVM_INFO @ 14587947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 39468467111238519686899094662064250272715636329028492145242965582847205362015 75
UVM_INFO @ 2022756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 45187962177534567931801323591705556519849962535947522048000713781258777959975 82
UVM_INFO @ 8639943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 22854998865979533917301506448286649832657694593026505407681890363752381979510 75
UVM_INFO @ 3850892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 37126187952354588122498171491987480319247650760520219097151809379735529676690 76
UVM_INFO @ 7849376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 20725878227534179678643489691120440776713354865842369847167977585435375208999 74
UVM_INFO @ 4204681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 98171101945738988552553247667251788398042322453894714919379947451390788019090 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 78693526365482723472180290742879317811331786425219295386564969711209185171750 87
UVM_INFO @ 16361712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_csr_rw 115517027902217312921324833286528878273720389048793567927729667034182737472811 76
UVM_INFO @ 3681407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 65652830117217229757042644087048895081325742419645448356950746282083068117687 75
UVM_INFO @ 2149943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 103414521798147825393390854466779444496595492621238268692456498160328814688332 76
UVM_INFO @ 7187269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---