Simulation Results: csrng

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.06 %
  • code
  • 90.33 %
  • assert
  • 92.14 %
  • func
  • 45.72 %
  • block
  • 95.11 %
  • line
  • 95.74 %
  • branch
  • 88.31 %
  • toggle
  • 91.55 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 72.860us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 22.474us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 15.772us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 31.000s 2054.318us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 144.746us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 112.283us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 15.772us 1 1 100.00
csrng_csr_aliasing 4.000s 144.746us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
alerts 1 1 100.00
csrng_alert 14.000s 401.671us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 6.000s 167.970us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 6.000s 167.970us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 2.000s 43.529us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 3.000s 63.282us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 16.164us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 358.461us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 358.461us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 22.474us 1 1 100.00
csrng_csr_rw 1.000s 15.772us 1 1 100.00
csrng_csr_aliasing 4.000s 144.746us 1 1 100.00
csrng_same_csr_outstanding 2.000s 43.587us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 22.474us 1 1 100.00
csrng_csr_rw 1.000s 15.772us 1 1 100.00
csrng_csr_aliasing 4.000s 144.746us 1 1 100.00
csrng_same_csr_outstanding 2.000s 43.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 258.913us 1 1 100.00
csrng_tl_intg_err 4.000s 83.904us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 3.000s 174.910us 1 1 100.00
csrng_csr_rw 1.000s 15.772us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 14.000s 401.671us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 2.000s 43.529us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
csrng_sec_cm 4.000s 258.913us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
csrng_sec_cm 4.000s 258.913us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
csrng_sec_cm 4.000s 258.913us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
csrng_sec_cm 4.000s 258.913us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
csrng_sec_cm 4.000s 258.913us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 14.000s 401.671us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 2.000s 43.529us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 14.000s 401.671us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 83.904us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
csrng_sec_cm 4.000s 258.913us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
csrng_sec_cm 4.000s 258.913us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 9.000s 728.411us 1 1 100.00
csrng_err 3.000s 77.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 230.000s 12308.870us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 46344629562813505350450503372673235363730237777525298466595603629495660644264 100
UVM_INFO @ 167969588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 112195066487276247606922726688257215768131729510377840609924270134221383400989 274
UVM_INFO @ 12308869555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---