Simulation Results: dma

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.60 %
  • code
  • 90.38 %
  • assert
  • 96.40 %
  • func
  • 61.02 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 290.056us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 1104.184us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 645.508us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 80.067us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 78.772us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 13.000s 6689.057us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 6.000s 1991.785us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 719.519us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 78.772us 1 1 100.00
dma_csr_aliasing 6.000s 1991.785us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 125.000s 7911.887us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 171.000s 14650.011us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 1074.000s 111305.952us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 1074.000s 111305.952us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 171.000s 14650.011us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 126.000s 25986.971us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 1074.000s 111305.952us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 2.000s 126.504us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 246.000s 38719.150us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 18.751us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 16.210us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 105.780us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 105.780us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 80.067us 1 1 100.00
dma_csr_rw 2.000s 78.772us 1 1 100.00
dma_csr_aliasing 6.000s 1991.785us 1 1 100.00
dma_same_csr_outstanding 3.000s 211.159us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 80.067us 1 1 100.00
dma_csr_rw 2.000s 78.772us 1 1 100.00
dma_csr_aliasing 6.000s 1991.785us 1 1 100.00
dma_same_csr_outstanding 3.000s 211.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 21.000s 1539.095us 1 1 100.00
dma_generic_stress 126.000s 25986.971us 1 1 100.00
dma_handshake_stress 1074.000s 111305.952us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 364.321us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 96.419us 1 1 100.00
dma_sec_cm 1.000s 35.863us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 53.000s 3200.638us 1 1 100.00
dma_longer_transfer 3.000s 493.464us 1 1 100.00
dma_stress_all_with_rand_reset 21.000s 1023.787us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 102811672454423339669304456658844010202568268815995767540346083610914321099728 146
UVM_INFO @ 1023786824ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---