Simulation Results: edn/edn0

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 78.12 %
  • code
  • 88.28 %
  • assert
  • 96.02 %
  • func
  • 50.07 %
  • block
  • 95.08 %
  • line
  • 97.42 %
  • branch
  • 89.26 %
  • toggle
  • 80.39 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 43.427us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 35.540us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 47.504us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 178.563us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 3.000s 42.781us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 72.715us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 47.504us 1 1 100.00
edn_csr_aliasing 3.000s 42.781us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 111.461us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 111.461us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 111.461us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 44.826us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.000s 88.392us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 38.708us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 12.118us 1 1 100.00
edn_disable_auto_req_mode 2.000s 44.877us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 7.000s 181.395us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 14.638us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 50.961us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 125.804us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 125.804us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 35.540us 1 1 100.00
edn_csr_rw 2.000s 47.504us 1 1 100.00
edn_csr_aliasing 3.000s 42.781us 1 1 100.00
edn_same_csr_outstanding 2.000s 247.637us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 35.540us 1 1 100.00
edn_csr_rw 2.000s 47.504us 1 1 100.00
edn_csr_aliasing 3.000s 42.781us 1 1 100.00
edn_same_csr_outstanding 2.000s 247.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.000s 625.106us 1 1 100.00
edn_tl_intg_err 2.000s 46.788us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 16.524us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.000s 88.392us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 625.106us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 625.106us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 625.106us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 625.106us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.000s 88.392us 1 1 100.00
edn_sec_cm 5.000s 625.106us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.000s 88.392us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 46.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 44.000s 5339.400us 1 1 100.00