Simulation Results: edn/edn1

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.82 %
  • code
  • 81.35 %
  • assert
  • 98.44 %
  • func
  • 80.67 %
  • line
  • 97.72 %
  • branch
  • 92.42 %
  • cond
  • 88.77 %
  • toggle
  • 86.91 %
  • FSM
  • 40.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.890s 42.290us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.750s 57.059us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.930s 26.387us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.040s 2069.201us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.070s 60.388us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.770s 49.347us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.930s 26.387us 1 1 100.00
edn_csr_aliasing 1.070s 60.388us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.150s 44.655us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.150s 44.655us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.150s 44.655us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.870s 40.560us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.050s 57.707us 1 1 100.00
errs 1 1 100.00
edn_err 1.030s 29.976us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 33.594us 1 1 100.00
edn_disable_auto_req_mode 1.110s 30.151us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.640s 215.540us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 15.194us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 41.077us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.650s 33.913us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.650s 33.913us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.750s 57.059us 1 1 100.00
edn_csr_rw 0.930s 26.387us 1 1 100.00
edn_csr_aliasing 1.070s 60.388us 1 1 100.00
edn_same_csr_outstanding 1.530s 335.106us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.750s 57.059us 1 1 100.00
edn_csr_rw 0.930s 26.387us 1 1 100.00
edn_csr_aliasing 1.070s 60.388us 1 1 100.00
edn_same_csr_outstanding 1.530s 335.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.380s 339.115us 1 1 100.00
edn_tl_intg_err 1.360s 557.595us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.850s 31.195us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.050s 57.707us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.380s 339.115us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.380s 339.115us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.380s 339.115us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.380s 339.115us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.050s 57.707us 1 1 100.00
edn_sec_cm 2.380s 339.115us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.050s 57.707us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.360s 557.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 36.770s 8250.881us 1 1 100.00